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MPC8379ECZQAJDA Datasheet(PDF) 6 Page - Freescale Semiconductor, Inc

Part # MPC8379ECZQAJDA
Description  PowerQUICC??II Pro Processor Hardware Specifications
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8379ECZQAJDA Datasheet(HTML) 6 Page - Freescale Semiconductor, Inc

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MPC8379E PowerQUICCII Pro Processor Hardware Specifications, Rev. 2
6
Freescale Semiconductor
Electrical Characteristics
1.10
Serial ATA (SATA) Controllers
The serial ATA (SATA) controllers have the following features:
Supports Serial ATA Rev 2.5 Specification
Spread spectrum clocking on receive
Asynchronous notification
Hot Plug including asynchronous signal recovery
Link power management
Native command queuing
Staggered spin-up and port multiplier support
Port multiplier support
SATA 1.5 and 3.0 Gb/s operation
Interrupt driven
Power management support
Error handling and diagnostic features
— Far end/near end loopback
— Failed CRC error reporting
— Increased ALIGN insertion rates
Scrambling and CONT override
1.11
Enhanced Secured Digital Host Controller (eSDHC)
The enhanced SD Host Controller (eSDHC) has the following features:
Conforms to SD Host Controller Standard Specification, Rev 2.0 with Test Event register support.
Compatible with the MMC System Specification, Rev 4.0
Compatible with the SD Memory Card Specification, Rev 2.0, and supports High Capacity SD
memory cards
Compatible with the SDIO Card Specification Rev, 1.2
Designed to work with SD Memory, miniSD Memory, SDIO, miniSDIO, SD Combo, MMC,
MMCplus, MMC 4x, and RS-MMC cards
SD bus clock frequency up to 50 MHz
Supports 1-/4-bit SD and SDIO modes, 1-/4-bit MMC modes
Supports internal DMA capabilities
2
Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the
MPC8379E. The device is currently targeted to these specifications. Some of these specifications are
independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer
design specifications.


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