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PCIMX514AJM6C Datasheet(PDF) 9 Page - Freescale Semiconductor, Inc |
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PCIMX514AJM6C Datasheet(HTML) 9 Page - Freescale Semiconductor, Inc |
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9 / 160 page  Features i.MX51A Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 9 Preliminary—Subject to Change Without Notice SJC Secure JTAG Interface System Control Peripherals JTAG manipulation is a known hacker’s method of executing unauthorized program code, getting control over secure applications, and running code in privileged modes. The JTAG port provides a debug access to several hardware blocks including the ARM processor and the system bus. The JTAG port must be accessible during platform initial laboratory bring-up, manufacturing tests and troubleshooting, as well as for software debugging by authorized entities. However, in order to properly secure the system, unauthorized JTAG usage should be strictly forbidden. In order to prevent JTAG manipulation while allowing access for manufacturing tests and software debugging, the i.MX51A processor incorporates a mechanism for regulating JTAG access. The i.MX51A Secure JTAG Controller provides four different JTAG security modes that can be selected via e-fuse configuration. SPBA Shared Peripheral Bus Arbiter System Control Peripherals SPBA (Shared Peripheral Bus Arbiter) is a two-to-one IP bus interface (IP bus) arbiter. SPDIF Sony Philips Digital Interface Multimedia Peripherals A standard digital audio transmission protocol developed jointly by the Sony and Philips corporations. Only the transmitter functionality is supported. SRTC Secure Real Time Clock Security The SRTC incorporates a special System State Retention Register (SSRR) that stores system parameters during system shutdown modes. This register and all SRTC counters are powered by dedicated supply rail NVCC_SRTC_POW. The NVCC_SRTC_POW can be energized even if all other supply rails are shut down. The power for this block comes from NVCC_SRTC_POW supply. When this supply is driven by the MC13892 power management controller, this block can be power backed up via the coin-cell feature of the MC13892.This register is helpful for storing warm boot parameters. The SSRR also stores the system security state. In case of a security violation, the SSRR mark the event (security violation indication). SSI-1 I2S/SSI/AC97 Interface Connectivity Peripherals The SSI is a full-duplex synchronous interface used on the i.MX51A processor to provide connectivity with off-chip audio peripherals. The SSI interfaces connect internally to the AUDMUX which interfaces to the i.MX51 system memory. The SSI supports a wide variety of protocols (SSI normal, SSI network, I2S, and AC-97), bit depths (up to 24 bits per word), and clock/frame sync options. Each SSI has two pairs of 8x24 FIFOs and hardware support for an external DMA controller in order to minimize its impact on system performance. The second pair of FIFOs provides hardware interleaving of a second audio stream, which reduces CPU overhead in use cases where two timeslots are being used simultaneously. SSI-2 SSI-3 TVE TV Encoder Multimedia The TVE is implemented in conjunction with the Image Processing Unit (IPU) allowing handheld devices to display captured still images and video directly on a TV or LCD projector. It supports the following analog video outputs: composite, S-video, and component video up to HD720p/1080i. Table 2. i.MX51A Digital and Analog Modules (continued) Block Mnemonic Block Name Subsystem Brief Description |
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