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MPC8378EZQAFDA Datasheet(PDF) 7 Page - Freescale Semiconductor, Inc |
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MPC8378EZQAFDA Datasheet(HTML) 7 Page - Freescale Semiconductor, Inc |
7 / 126 page MPC8378E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 7 Electrical Characteristics 2.1.1 Absolute Maximum Ratings Table 2 provides the absolute maximum ratings. Table 2. Absolute Maximum Ratings 1 Characteristic Symbol Max Value Unit Notes Core supply voltage VDD –0.3 to 1.1 V — PLL supply voltage (e300 core, system and eLBC) AVDD –0.3 to 1.1 V — DDR1 and DDR2 DRAM I/O voltage GVDD –0.3 to 2.75 –0.3 to 1.98 V— Three-speed Ethernet I/O, MII management voltage LVDD[1,2] –0.3 to 3.63 V — PCI, DUART, system control and power management, I2C, and JTAG I/O voltage OVDD –0.3 to 3.63 V — Local bus LBVDD –0.3 to 3.63 V — SerDes L[1,2]_ nVDD –0.3 to 1.1 V 6 Input voltage DDR DRAM signals MVIN –0.3 to (GVDD + 0.3) V 2, 4 DDR DRAM reference MVREF –0.3 to (GVDD + 0.3) V 2, 4 Three-speed Ethernet signals LVIN –0.3 to (LVDD + 0.3) V — PCI, DUART, CLKIN, system control and power management, I2C, and JTAG signals OVIN –0.3 to (OVDD + 0.3) V 3, 4 Local Bus LBIN –0.3 to (LBVDD + 0.3) V 5 Storage temperature range TSTG –55 to 150 °C— Notes: 1 Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2 Caution: MV IN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 3 Caution: OV IN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4 (M,O)V IN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2. 5 OV IN on the PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as shown in Figure 2. 6 L[1,2]_nV DD includes SDAVDD_0, XCOREVDD, and XPADVDD power inputs. |
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