SY898533L

Precision Differential 3.3V Low Skew

LVPECL 1:4 Fanout Buffer

Precision Edge is a registered trademark of Micrel, Inc.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (

July 2009

M9999-072409-C

General Description

The SY898533L is a 3.3V, low skew, 1:4 LVPECL fanout

buffer with two selectable clock input pairs. Most standard

differential input levels can be applied to the CLK, /CLK

pair while LVPECL, CML, or SSTL input levels can be

applied to the PCLK, /PCLK pair. To eliminate runt pulses

on the outputs during asynchronous assertion/de-assertion

of the clock enable pin, the clock enable is synchronized

with the input signal.

The SY898533L operates from a 3.3V ±5% supply and is

guaranteed over the full industrial temperature range of

0°C to +70°C. The SY898533L is part of Micrel’s high-

speed, Precision Edge

Datasheets and support documentation can be found on

Micrel’s web site at: www.micrel.com.

Functional Block Diagram

Precision Edge

®

Features

∑ Provides four differential 3.3V LVPECL copies

∑ Selects between differential CLK, /CLK or LVPECL clock

inputs

∑ CLK, /CLK pair accepts LVDS, LVPECL, LVHSTL,

SSTL, HCSL input levels

∑ PCLK, /PCLK pair accepts LVPECL, CML, SSTL input

levels

∑ Guaranteed AC performance over temperature and

supply voltage:

650MHz Maximum output frequency

< 1.4ns Propagation delay (In-to-Q)

< 30ps Output skew

< 150ps Part-to-part skew

Additive phase jitter, RMS: 0.06ps (typical)

∑ 3.3V ±5% supply voltage

∑ 0°C to +70°C temperature operating range

∑ Available in a 20-pin TSSOP package

Applications

∑ SONET clock distribution

∑ Backplane distribution

Markets

∑ LAN/WAN

∑ Enterprise servers

∑ ATE

∑ Test and measurement