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AD9231-40EBZ Datasheet(PDF) 10 Page - Analog Devices |
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AD9231-40EBZ Datasheet(HTML) 10 Page - Analog Devices |
10 / 36 page AD9231 Rev. 0 | Page 10 of 36 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK+ CLK– SYNC NC NC NC NC (LSB) D0B D1B DRVDD D2B D3B D4B D5B D6B D7B PDWN OEB CSB SCLK/DFS SDIO/DCS ORA D11A (MSB) D10A D9A D8A D7A DRVDD D6A D5A D4A D3A 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB GROUND TO ENSURE PROPER HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS. AD9231 TOP VIEW (Not to Scale) Figure 5. Pin Configuration Table 8. Pin Function Description Pin No. Mnemonic Description 0 GND Exposed paddle is the only ground connection for the chip. Must be connected to PCB AGND. 1, 2 CLK+, CLK− Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs. 3 SYNC Digital Input. SYNC input to clock divider. 30 kΩ internal pull-down. 4, 5, 6, 7, 25, 26, 27, 29 NC Do Not Connect. 8 to 9, 11 to 18, 20, 21 D0B to D11B Channel B Digital Outputs. D11B = MSB. 10, 19, 28, 37 DRVDD Digital Output Driver Supply (1.8 V to 3.3 V). 22 ORB Channel B Out-of-Range Digital Output. 23 DCOB Channel B Data Clock Digital Output. 24 DCOA Channel A Data Clock Digital Output. 30 to 36, 38 to 42 D0A to D11A Channel A Digital Outputs. D11A = MSB. 43 ORA Channel A Out-of-Range Digital Output. 44 SDIO/DCS SPI Data Input/Output (SDIO). Bidirectional SPI Data I/O in SPI mode. 30 kΩ internal pull- down in SPI mode. Duty Cycle Stabilizer (DCS). Static enable input for duty cycle stabilizer in non-SPI mode. 30 kΩ internal pull-up in non-SPI (DCS) mode. 45 SCLK/DFS SPI Clock (SCLK) Input in SPI mode. 30 kΩ internal pull-down. Data Format Select (DFS). Static control of data output format in non-SPI mode. 30 kΩ internal pull-down. DFS high = twos complement output. DFS low = offset binary output. 46 CSB SPI Chip Select. Active low enable; 30 kΩ internal pull-up. 47 OEB Digital Input. Enable Channel A and Channel B digital outputs if low, tristate outputs if high. 30 kΩ internal pull-down. 48 PDWN Digital Input. 30 kΩ internal pull-down. PDWN high = power-down device. PDWN low = run device, normal operation. |
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