Integrated Silicon Solution, Inc.

5

Preliminary Information Rev. 00A

08/25/09

IS25C08B

WRITE ENABLE (WREN)

When Vcc is initially applied, the device powers up with

both status register and entire array in a write-disabled

state. Upon completion of Write Disable (WRDI),

Write Status Register (WRSR), or Write Data to Array

(WRITE), the device resets the WEN bit in the Status

Register to 0. Prior to any data modification, a WREN

instruction is necessary to set WEN to 1. (See Figure 2

for timing).

WRITE DISABLE (WRDI)

The device can be completely protected from modifica-

tion by resetting WEN to 0 through the WRDI instruc-

tion. (See Figure 3 for timing).

READ STATUS REGISTER (RDSR)

The Read Status instruction tells the user the status of

Write Protect Enable, the Block Protection setting (see

Table 2), the Write Enable state, and the RDY status.

RDSR is the only instruction accepted when a write

cycle is underway. It is recommended that the status

of Write Enable and RDY be checked, especially prior

to an attempted modification of data. The 8 bits of the

Status Register can be repeatedly output on SO after

the initial Op-code. (See Figure 4 for timing).

Table 3. Instruction Set

Name

Op-code

Operation

Address

Data(SI)

Data (SO)

WREN 0000X110

SetWriteEnableLatch

-

-

-

WRDI

0000X100

ResetWriteEnableLatch

-

-

-

RDSR 0000X101

ReadStatusRegister

-

-

D7-D0,...

WRSR 0000X001

WriteStatusRegister

-

D7-D0

-

READ

0000X011

ReadDatafromArray

A15-A0

-

D7-D0,...

WRITE 0000X010

WriteDatatoArray

A15-A0

D7-D0,...

-

DEVICE OPERATION

3). To begin an instruction, the chip select (CS) should be dropped Low. Subsequently, each Low-to-High transition

of the clock (SK) will latch a stable value on the SI pin. After the 8-bit op-code, it may be appropriate to continue to

input an address or data to SI, or to output data from SO. During data output, values appear on the falling edge of

SK. All bits are transferred with MSB first. Upon the last bit of communication, but prior to any following Low-to-High

transition of SK, CS should be raised High to end the transaction. The device then would enter Standby Mode if no

internal programming were underway.

1. X = Don’t care bit. For consistency, it is best to use “0”.

2. Some address bits are don’t care. See Table 5.

3. If the bits clocked-in for an op-code are invalid, SO remains high impedance, and upon CS going High there is no

affect. A valid op-code with an invalid number of bits clocked-in for address or data will cause an attempt to modify

the array or Status Register to be ignored.