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IS42S16400F-6TL Datasheet(PDF) 2 Page - Integrated Silicon Solution, Inc |
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IS42S16400F-6TL Datasheet(HTML) 2 Page - Integrated Silicon Solution, Inc |
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2 / 58 page  2 Integrated Silicon Solution, Inc. — www.issi.com Rev. F 11/09/09 IS42S16400F IS45S16400F GENERAL DESCRIPTION The 64Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V memory systems containing 67,108,864 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 16,777,216-bit bank is organized as 4,096 rows by 256 columns by 16 bits. The64MbSDRAMincludesanAUTOREFRESHMODE, and a power-saving, power-down mode. All signals are registeredonthepositiveedgeoftheclocksignal,CLK. AllinputsandoutputsareLVTTLcompatible. The64MbSDRAMhastheabilitytosynchronouslyburst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access. A self-timed row precharge initiated at the end of the burst sequenceisavailablewiththeAUTOPRECHARGEfunction enabled. Precharge one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. SDRAM read and write accesses are burst oriented starting at a selected location and continuing for a programmed number of locations in a programmed sequence.The registration of an ACTIVE command begins accesses, followedbyaREADorWRITEcommand.TheACTIVE command in conjunction with address bits registered are usedtoselectthebankandrowtobeaccessed(BA0, BA1selectthebank;A0-A11selecttherow).TheREAD or WRITE commands in conjunction with address bits registered are used to select the starting column location for the burst access. ProgrammableREADorWRITEburstlengthsconsistof 1, 2, 4 and 8 locations, or full page, with a burst terminate option. CLK CKE CS RAS CAS WE A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BA0 BA1 A11 COMMAND DECODER & CLOCK GENERATOR MODE REGISTER REFRESH CONTROLLER REFRESH COUNTER SELF REFRESH CONTROLLER ROW ADDRESS LATCH COLUMN ADDRESS LATCH BURST COUNTER COLUMN ADDRESS BUFFER COLUMN DECODER DATA IN BUFFER DATA OUT BUFFER DQM DQ 0-15 VDD/VDDQ GND/GNDQ 12 12 8 12 12 8 16 16 16 16 256K (x 16) 4096 4096 4096 4096 MEMORY CELL ARRAY BANK 0 SENSE AMP I/O GATE BANK CONTROL LOGIC ROW ADDRESS BUFFER FUNCTIONAL BLOCK DIAGRAM |
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