PRELIMINARY
CY2XF33
Document Number: 001-53148 Rev. *B
Page 3 of 7
Absolute Maximum Conditions
Parameter
Description
Condition
Min
Max
Unit
VDD
Supply Voltage
–0.5
4.4
V
VIN[1]
Input Voltage, DC
Relative to VSS
–0.5
VDD+0.5
V
TS
Temperature, Storage
Non operating
–55
135
°C
TJ
Temperature, Junction
–40
135
°C
ESDHBM
ESD Protection (Human Body Model)
JEDEC STD 22-A114-B
2000
–
V
ΘJA[2]
Thermal Resistance, Junction to Ambient
0 m/s airflow
64
°C/W
Operating Conditions
Parameter
Description
Min
Typ
Max
Unit
VDD
3.3V Supply Voltage Range
3.135
3.3
3.465
V
2.5V Supply Voltage Range
2.375
2.5
2.625
V
TPU
Power Up Time for VDD to Reach Minimum Specified Voltage (Power Ramp
is Monotonic)
0.05
–
500
ms
TA
Ambient Temperature (Commercial)
0
–
70
°C
Ambient Temperature (Industrial)
–40
–
85
°C
Notes
1. The voltage on any input or IO pin cannot exceed the power pin during power up.
2. Simulated. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). The internal layers
are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model.
3. IDD includes ~4 mA of current that is dissipated externally in the output termination resistors.
4. Not 100% tested, guaranteed by design and characterization.
DC Electrical Characteristics
Parameter
Description
Condition
Min
Typ
Max
Unit
IDD[3]
Operating Supply Current
VDD = 3.465V, CLK = 150 MHz, output
terminated
–
–
120
mA
VDD = 2.625V, CLK = 150 MHz, output
terminated
––
115
mA
VOD
LVDS Differential Output Voltage
VDD = 3.3V or 2.5V, defined in Figure 3
as terminated in Figure 2
247
–
454
mV
ΔVOD
Change in VOD between Comple-
mentary Output States
VDD = 3.3V or 2.5V, defined in Figure 3
as terminated in Figure 2
––
50
mV
VOS
LVDS Offset Output Voltage
VDD = 3.3V or 2.5V, defined in Figure 4
as terminated in Figure 2
1.125
–
1.375
V
ΔVOS
Change in VOS between Comple-
mentary Output States
VDD = 3.3V or 2.5V, RTERM = 100Ω
between CLK and CLK#
––
50
mV
VIH
Input High Voltage
0.7*VDD
––
V
VIL
Input Low Voltage
–
–
0.3*VDD
V
IIH0
Input High Current, FS0 pin
Input = VDD
––
115
μA
IIH1
Input High Current, FS1 pin
Input = VDD
––
10
μA
IIL0
Input Low Current, FS0 pin
Input = VSS
–50
–
–
μA
IIL1
Input Low Current, FS1 pin
Input = VSS
–20
–
–
μA
CIN0[4]
Input Capacitance, FS0 pin
–
15
–
pF
CIN1[4]
Input Capacitance, FS1 pin
–
4
–
pF
[+] Feedback
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
