Integrated Silicon Solution, Inc.

7

Rev. A

05/14/09

72 Mb (2M x 36 & 4M x 18)

DDR-II (Burst of 4) CIO Synchronous SRAMs

The Timing Reference Diagram for Truth Table on page

8 is helpful in understanding the clock and write truth

tables, as it shows the cycle relationship between clocks, address, data-in, data-out, and controls. All read

State Diagram

Linear Burst Sequence Table

Burst Sequence

Case 1

Case 2

Case 3

Case 4

First Address

000

11011

Second Address

011

01100

Third Address

101

10001

Fourth Address

110

00110

Power Up

DDR

-II Write

NOP

DDR

-II Read

Write

Write

Notes: 1. Internal burst counter is fixed as four-bit linear; that is, when first address is A0+0, next internal burst address is A0+1.

2. Read refers to read active status with R/W = high.

4. Load refers to read new address active status with LD = low.

3. Write refers to write active status with R/W = low.

Load New Address

Load

Load

Read

Load

Load

Load

5. Load is read new address inactive status with LD = high.

Increment

Increment

Always

Always

Write

Read

Read Address

Write Address

Dcount = 1

Dcount = 1

Dcount = 0

Dcount = 2

Load

Dcount = 2

Dcount = Dcount + 1

Dcount = Dcount + 1