IS61DDB24M18-250M3 datasheet(9/25 Pages) ISSI

Part #	IS61DDB24M18-250M3

Description	72 Mb (2M x 36 & 4M x 18) DDR-II (Burst of 2) CIO Synchronous SRAMs

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Manufacturer	ISSI [Integrated Silicon Solution, Inc]

Direct Link	http://www.issi.com

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9 / 25 page

Integrated Silicon Solution, Inc.

9

Rev. B

11/10/09

72 Mb (2M x 36 & 4M x 18)

DDR-II (Burst of 2) CIO Synchronous SRAMs

X36 Write Truth Table Use the following table with the Timing Reference Diagram for Truth Table on

page

8.

Operation

K

(tw)

K

(tw + 0.5)

BW0

BW1

BW2

BW3

DB

DB+1

Write Byte 0

L

→

L

H

D0-8 (tw + 1)

Write Byte 1

L

→H

H

L

H

D9-17 (tw + 1)

Write Byte 2

L

→H

H

L

H

D18-26 (tw + 1)

Write Byte 3

L

→H

H

L

D27-35 (tw + 1)

Write All Bytes

L

→H

L

D0-35 (tw + 1)

Abort Write

L

→H

H

Don’t care

Write Byte 0

L

→H

L

H

D0-8 (tw + 1.5)

Write Byte 1

L

→H

H

L

H

D9-17 (tw+1.5)

Write Byte 2

L

→H

H

L

H

D18-26 (tw+1.5)

Write Byte 3

L

→H

HHH

L

D27-35 (tw+1.5)

Write All Bytes

L

→H

L

D0-35 (tw+1.5)

Abort Write

L

→H

HHH

H

Don’t care

Notes;

1. For all cases. R/W must be active low during the rising edge of K occurring at time tW.

2. For timing definitions, refer to the AC Characteristics on page

15. Signals must have AC specifications with respect to switching

clocks K and K.

X18 Write Truth Table (Use this table with the Timing Reference Diagram for Truth Table on page

8.)

Operation

K

(tw)

K

(tw+0.5)

BW0

BW1

DB

DB+1

Write Byte 0 on B

L

→H

L

H

D0-8 (tw + 1)

Write Byte 1 on B

L

→H

H

L

D9–17 (tw + 1)

Write All Bytes on B

L

→H

L

D0–17 (tw + 1)

Abort Write on B

L

→H

H

Don’t care

Write Byte 1 on B+1

L

→H

L

H

D0–8 (tw + 1.5)

Write Byte 2 on B+1

L

→H

H

L

D9–17 (tw + 1.5)

Write All Bytes on B+1

L

→H

L

D0–17 (tw + 1.5)

Abort Write on B+1

L

→H

H

Don’t care

Notes;

1. Refer to Timing Reference Diagram for Truth Table on page

8. Cycle time starts at n and is referenced to the K clock.

2. For all cases, R/W must be active low during the rising edge of K occurring at tw.

3. For timing definitions, refer to the AC Characteristics on page

15. Signals must have AC specs with respect to switching clocks K

and K.

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IS61DDB24M18-250M3 Datasheet(PDF) 9 Page - Integrated Silicon Solution, Inc

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