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IS61LPS102436A-166B3 Datasheet(PDF) 9 Page - Integrated Silicon Solution, Inc |
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IS61LPS102436A-166B3 Datasheet(HTML) 9 Page - Integrated Silicon Solution, Inc |
9 / 21 page Integrated Silicon Solution, Inc. 9 Rev. B 03/27/08 IS61VPS102436A, IS61LPS102436A,IS61VPS204818A,IS61LPS204818A PARTIAL TRUTH TABLE Function GW GW GW GW GW BWE BWE BWE BWE BWE BWa BWa BWa BWa BWa BWb BWb BWb BWb BWb BWc BWc BWc BWc BWc BWd BWd BWd BWd BWd Read H H X X X X Read H L H H H H Write Byte 1 H L L H H H Write All Bytes H L L L L L Write All Bytes L X X X X X TRUTH TABLE(1-8) (1CE option) NEXT CYCLE ADDRESS CE CE CE CE CE ADSP ADSP ADSP ADSP ADSP ADSC ADSC ADSC ADSC ADSC ADV ADV ADV ADV ADV WRITE WRITE WRITE WRITE WRITE OE OE OE OE OE DQ Deselected None H X L X X X High-Z Read, Begin Burst External L L X X X L Q Read, Begin Burst External L L XXXH High-Z Write, Begin Burst External L H L X L X D Read, Begin Burst External L H L X H L Q Read, Begin Burst External L H L X H H High-Z Read, Continue Burst Next X H H L H L Q Read, Continue Burst Next X H H L H H High-Z Read, Continue Burst Next H X H L H L Q Read, Continue Burst Next H X H L H H High-Z Write, Continue Burst Next X H H L L X D Write, Continue Burst Next H X H L L X D Read, Suspend Burst Current X H H H H L Q Read, Suspend Burst Current X H HHHH High-Z Read, Suspend Burst Current H X H H H L Q Read, Suspend Burst Current H X HHHH High-Z Write, Suspend Burst Current X H H H L X D Write, Suspend Burst Current H X H H L X D NOTE: 1. X means “Don’t Care.” H means logic HIGH. L means logic LOW. 2. For WRITE, L means one or more byte write enable signals (BWa-h) and BWE are LOW or GW is LOW. WRITE = H for all BWx, BWE, GW HIGH. 3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and DQPc. BWd enables WRITEs to DQd’s and DQPd. DQPa-DQPd are available on the x36 version. 4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5. Wait states are inserted by suspending burst. 6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification. |
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