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IS61LF204818A-7.5TQLI Datasheet(PDF) 8 Page - Integrated Silicon Solution, Inc |
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IS61LF204818A-7.5TQLI Datasheet(HTML) 8 Page - Integrated Silicon Solution, Inc |
8 / 20 page 8 Integrated Silicon Solution, Inc. Rev. B 04/17/08 IS61LF102436A IS61LF204818A IS61VF102436A IS61VF204818A TRUTH TABLE(1-8) (3CEoption) OPERATION ADDRESS CE CE2 CE2 ZZ ADSP ADSC ADV WRITE OE CLK DQ DeselectCycle,Power-Down None H X X L X L X X X L-H High-Z DeselectCycle,Power-Down None L X L L L X X X X L-H High-Z DeselectCycle,Power-Down None L H X L L X X X X L-H High-Z DeselectCycle,Power-Down None L X L L H L X X X L-H High-Z DeselectCycle,Power-Down None L H X L H L X X X L-H High-Z SnoozeMode,Power-Down None X X X H X X X X X X High-Z ReadCycle,BeginBurst External L L H L L X X X L L-H Q ReadCycle,BeginBurst External L L H L L X X X H L-H High-Z WriteCycle,BeginBurst External L L H L H L X L X L-H D ReadCycle,BeginBurst External L L H L H L X H L L-H Q ReadCycle,BeginBurst External L L H L H L X H H L-H High-Z ReadCycle,ContinueBurst Next X X X L H H L H L L-H Q ReadCycle,ContinueBurst Next X X X L H H L H H L-H High-Z ReadCycle,ContinueBurst Next H X X L X H L H L L-H Q ReadCycle,ContinueBurst Next H X X L X H L H H L-H High-Z WriteCycle,ContinueBurst Next X X X L H H L L X L-H D WriteCycle,ContinueBurst Next H X X L X H L L X L-H D ReadCycle,SuspendBurst Current X X X L H H H H L L-H Q ReadCycle,SuspendBurst Current X X X L H H H H H L-H High-Z ReadCycle,SuspendBurst Current H X X L X H H H L L-H Q ReadCycle,SuspendBurst Current H X X L X H H H H L-H High-Z WriteCycle,SuspendBurst Current X X X L H H H L X L-H D WriteCycle,SuspendBurst Current H X X L X H H L X L-H D NOTE: 1. Xmeans“Don’tCare.”HmeanslogicHIGH.LmeanslogicLOW. 2. For WRITE, L means one or more byte write enable signals (BWa-h) and BWEareLOWorGWisLOW.WRITE = H for all BWx , BWE, GWHIGH. 3. BWaenablesWRITEstoDQa’sandDQPa.BWbenablesWRITEstoDQb’sandDQPb.BWcenablesWRITEstoDQc’s and DQPc.BWdenablesWRITEstoDQd’sandDQPd.BWeenablesWRITEstoDQe’sandDQPe.BWfenablesWRITEstoDQf’s andDQPf.BWgenablesWRITEstoDQg’sandDQPg.BWhenablesWRITEstoDQh’sandDQPh.DQPa-DQPhareavailable onthex72version.DQPaandDQPbareavailableonthex18version. DQPa-DQPdareavailableonthex36version. 4. All inputs except OEandZZmustmeetsetupandholdtimesaroundtherisingedge(LOWtoHIGH)ofCLK. 5. Waitstatesareinsertedbysuspendingburst. 6. ForaWRITEoperationfollowingaREADoperation,OEmustbeHIGHbeforetheinputdatasetuptimeandheldHIGHduring the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSPLOWalwaysinitiatesaninternalREADattheL-HedgeofCLK.AWRITEisperformedbysettingoneormorebytewrite enable signals and BWELOWorGWLOWforthesubsequentL-HedgeofCLK.SeeWRITEtimingdiagramforclarification. |
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