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IS61QDB22M36-300M3 Datasheet(PDF) 9 Page - Integrated Silicon Solution, Inc |
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IS61QDB22M36-300M3 Datasheet(HTML) 9 Page - Integrated Silicon Solution, Inc |
9 / 27 page Integrated Silicon Solution, Inc. — 1-800-379-4774 9 Rev. A 05/14/09 72 Mb (2M x 36 & 4M x 18) QUAD (Burst of 2) Synchronous SRAMs X36 Write Truth Table Use the following table with the Timing Reference Diagram for Truth Table on page 8. Operation K(t) K (t + 0.5) BW0 BW1 BW2 BW3 DB DB+1 Write Byte 0 L →H L H H H D0-8 (t) Write Byte 1 L →H H L H H D9-17 (t) Write Byte 2 L →H H H L H D18-26 (t) Write Byte 3 L →H H H H L D27-35 (t) Write All Bytes L →H L L L L D0-35 (t) Abort Write L →H HHH H Don’t care Write Byte 0 L →H L H H H D0-8 (t + 0.5) Write Byte 1 L →H H L H H D9-17 (t + 0.5) Write Byte 2 L →H H H L H D18-26 (t + 0.5) Write Byte 3 L →H H H H L D27-35 (t + 0.5) Write All Bytes L →H L L L L D0-35 (t + 0.5) Abort Write L →H HHH H Don’t care Notes; 1. For all cases. W must be active low during the rising edge of K occurring at time t. 2. For timing definitions, refer to the AC Characteristics on page 15,16. Signals must have AC specifications with respect to switching clocks K and K. X18 Write Truth Table (Use this table with the Timing Reference Diagram for Truth Table on page 8.) Operation K(t) K (t + 0.5) BW0 BW1 DB DB+1 Write Byte 0 on B L →HL H D0–8 (t) Write Byte 1 on B L →HH L D9–17 (t) Write All Bytes on B L →HL L D0–17 (t) Abort Write on B L →HH H Don’t care Write Byte 1 on B+1 L →HL H D0–8(t + 0.5) Write Byte 2 on B+1 L →HH L D9–17(t + 0.5) Write All Bytes on B+1 L →HL L D0–17(t + 0.5) Abort Write on B+1 L →HH H Don’t care Notes; 1. Refer to Timing Reference Diagram for Truth Table on page 8. Cycle time starts at n and is referenced to the K clock. 2. For all cases, W must be active low during the rising edge of K occurring at t. 3. For timing definitions, refer to the AC Characteristics on page 15,16. Signals must have AC specs with respect to switching clocks K and K. |
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