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IS61QDPB44M18-400M3 Datasheet(PDF) 11 Page - Integrated Silicon Solution, Inc |
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IS61QDPB44M18-400M3 Datasheet(HTML) 11 Page - Integrated Silicon Solution, Inc |
11 / 28 page Integrated Silicon Solution, Inc. 11 Rev. A 05/14/09 72 Mb (2M x 36 & 4M x 18) QUADP (Burst of 4) Synchronous SRAMs X18 Write Truth Table Use the following table with the Timing Reference Diagram for Truth Table on page 8. Operation K(t+1) K(t+1.5) K(t+2)K(t+2.5) BW0 BW1 DB DB+1 DB+2 DB+3 Write Byte 0 L →H L H D0-8 (t+1) Write Byte 1 L →H H L D9-17 (t+1) Write All Bytes L →H L L D0-17 (t+1) Abort Write L →H HH Don’t care Write Byte 0 L →H L H D0-8 (t+1.5) Write Byte 1 L →H H L D9-17 (t+1.5) Write All Bytes L →H L L D0-17 (t+1.5) Abort Write L →H HH Don’t care Write Byte 0 L →H L H D0-8 (t+2) Write Byte 1 L →H H L D9-17 (t+2) Write All Bytes L →H L L D0-17 (t+2) Abort Write L →H HH Don’t care Write Byte 0 L →H L H D0-8 (t+2.5) Write Byte 1 L →H H L D9-17 (t+2.5) Write All Bytes L →H L L D0-17 (t+2.5) Abort Write L →H HH Don’t care Notes; 1. For all cases. W needs to be active low during the rising edge of K occurring at time t. 2. For timing definitions refer to the AC Characteristics on page 17. Signals must have AC specifications with respect to switching clocks K and K. |
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