Integrated Silicon Solution, Inc.

11

Rev. A

05/14/09

72 Mb (2M x 36 & 4M x 18)

QUADP (Burst of 4) Synchronous SRAMs

page

8.

Operation

Write Byte 0

L

→H

L

H

Write Byte 1

L

→H

H

L

Write All Bytes

L

→H

L

L

Abort Write

L

→H

HH

Don’t care

Write Byte 0

L

→H

L

H

Write Byte 1

L

→H

H

L

Write All Bytes

L

→H

L

L

Abort Write

L

→H

HH

Don’t care

Write Byte 0

L

→H

L

H

Write Byte 1

L

→H

H

L

Write All Bytes

L

→H

L

L

Abort Write

L

→H

HH

Don’t care

Write Byte 0

L

→H

L

H

Write Byte 1

L

→H

H

L

Write All Bytes

L

→H

L

L

Abort Write

L

→H

HH

Don’t care

Notes;

1. For all cases. W needs to be active low during the rising edge of K occurring at time t.

2. For timing definitions refer to the AC Characteristics on page

17. Signals must have AC specifications with respect to switching

clocks K and K.