6

Integrated Silicon Solution, Inc.

Rev.

A

05/14/09

72 Mb (2M x 36 & 4M x 18)

QUADP (Burst of 4) Synchronous SRAMs

Application Example

SA

K K

D

Q

ZQ

SRAM #4

R=250

Ω

Vt

Data In

Data Out

Address

R

W

BW

Memory

Controller

Source CLK

Source CLK

SA

K K

D

Q

ZQ

SRAM #1

R=250

Ω

Vt

Vt

R

R=50

R

SRAM1 Input CQ

SRAM1 Input CQ

SRAM4 Input CQ

SRAM4 Input CQ

CQ

CQ

CQ

CQ

Power-Up and Power-Down Sequences

The following sequence is used for power-up:

1. The power supply inputs must be applied in the following order while keeping Doff in LOW logic state:

1) VDD

2) VDDQ

3) VREF

2. Start applying stable clock inputs (K, K, C, and C).

3. After clock signals have stabilized, change Doff to HIGH logic state.

4. Once the Doff is switched to HIGH logic state, wait an additional 1024 clock cycles to lock the DLL.

NOTES:

1. The power-down sequence must be done in reverse of the power-up sequence.

2. VDDQ can be allowed to exceed VDD by no more than 0.6V.

3. VREF can be applied concurrently with VDDQ.