1

Rev. 00A

09/25/09

IS62C10248AL

IS65C10248AL

Copyright © 2009 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no

liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on

any published information and before placing orders for products.

1M x 8 LOW VOLTAGE,

ULTRA LOW POWER CMOS STATIC RAM

FEATURES

• High-speedaccesstime:45ns,55ns

• CMOSlowpoweroperation

– 36 mW (typical) operating

–12µW(typical)CMOSstandby

• TTLcompatibleinterfacelevels

• Singlepowersupply

• Threestateoutputs

• Lead-freeavailable

FUNCTIONAL BLOCK DIAGRAM

PRELIMINARY INFORMATION

OCTOBER 2009

DESCRIPTION

The

speed, 8M bit static RAMs organized as 1M words by

8 bits. It is fabricated using

CMOStechnology.Thishighlyreliableprocesscoupled

with innovative circuit design techniques, yields high-

performance and low power consumption devices.

When CS1isHIGH(deselected)orwhenCS2isLOW

(deselected), the device assumes a standby mode at

which the power dissipation can be reduced down with

CMOSinputlevels.

Easy memory expansion is provided by using Chip Enable

andOutputEnableinputs.TheactiveLOWWriteEnable

(WE)

controls both writing and reading of the memory.

TheIS62C10248ALandIS65C10248ALarepackagedin

theJEDECstandard48-pinminiBGA(9mmx11mm)and

44-PinTSOP(TYPEII).

A0-A19

CS1

OE

WE

1M x 8

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

I/O

DATA

CIRCUIT

I/O0-I/O7

CS2