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LT3743EUFDTRPBF Datasheet(PDF) 10 Page - Linear Technology |
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LT3743EUFDTRPBF Datasheet(HTML) 10 Page - Linear Technology |
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10 / 28 page  LT3743 10 3743f PWMGL (Pin 22/Pin 23): The PWMGL output pin drives the gate of an external FET to connect one of the switch- ing regulator output capacitors to the load. The output impedance is approximately 2.5Ω. HG (Pin 23/Pin 24): HG is the top FET gate drive signal that controls the state of the high side external power FET. The driver impedance is 2.5Ω. SW (Pin 24/Pin 25): The SW pin is used internally as the lower rail for the floating high side driver. Externally, this node connects the two power FETs and the inductor. CBOOT (Pin 25/Pin 26): The CBOOT pin provides a float- ing 5V regulated supply for the high side FET driver. An external Schottky diode is required from the VCC_INT pin to the CBOOT pin to charge the CBOOT capacitor when the switch pin is near ground. PIN FUNCTIONS (QFN/TSSOP) LG (Pin 26/Pin 28): LG is the bottom FET gate drive signal that controls the state of the low side external power FET. The driver impedance is 2.5Ω. VCC_INT (Pin 27/Pin 1): A regulated 5V output for charging the CBOOT capacitor. VCC_INT also provides the power for the digital and switching subcircuits. Below 6V VIN, tie this pin to the rail. VCC_INT is current limited to ≈50mA. Shutdown operation disables the output voltage drive. VIN (Pin 28/Pin 3): Input Supply Pin. Must be locally bypassed with a 1μF low ESR capacitor to ground. |
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