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LTC2625IGN-1TRPBF Datasheet(PDF) 11 Page - Linear Technology |
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LTC2625IGN-1TRPBF Datasheet(HTML) 11 Page - Linear Technology |
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11 / 18 page  LTC2605/LTC2615/LTC2625 11 2605fa OPERATION Power-On Reset The LTC2605/LTC2615/LTC2625 clear the outputs to zero-scale when power is first applied, making system initialization consistent and repeatable. The LTC2605-1/ LTC2615-1/LTC2625-1 set the voltage outputs to mid-scale when power is first applied. For some applications, downstream circuits are active dur- ing DAC power-up, and may be sensitive to nonzero outputs from the DAC during this time. The LTC2605/LTC2615/ LTC2625 contain circuitry to reduce the power-on glitch: the analog outputs typically rise less than 10mV above zero-scale during power on if the power supply is ramped to 5V in 1ms or more. In general, the glitch amplitude decreases as the power supply ramp time is increased. See Power-On Reset Glitch in the Typical Performance Characteristics section. Power Supply Sequencing The voltage at REF (Pin 6) should be kept within the range –0.3V ≤ VREF ≤ VCC + 0.3V (see Absolute Maximum Rat- ings). Particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at VCC (Pin 16) is in transition. Transfer Function The digital-to-analog transfer function is: V k V OUT IDEAL N REF () = ⎛ ⎝⎜ ⎞ ⎠⎟ 2 where k is the decimal equivalent of the binary DAC input code, N is the resolution and VREF is the voltage at REF (Pin 6). Serial Digital Interface The LTC2605/LTC2615/LTC2625 communicate with a host using the standard 2-wire digital interface. The Tim- ing Diagram (Figure 1) shows the timing relationship of the signals on the bus. The two bus lines, SDA and SCL, must be high when the bus is not in use. External pull-up resistors or current sources are required on these lines. The value of these pull-up resistors is dependent on the power supply and can be obtained from the I2C specifica- tions. For an I2C bus operating in the fast mode, an active pull-up will be necessary if the bus capacitance is greater than 200pF. The VCC power should not be removed from the LTC2605/LTC2615/LTC2625 when the I2C bus is active to avoid loading the I2C bus lines through the internal ESD protection diodes. The LTC2605/LTC2615/LTC2625 are receive-only (slave) devices. The master can write to the LTC2605/LTC2615/ LTC2625. The LTC2605/LTC2615/LTC2625 do not respond to a read from the master. The START (S) and STOP (P) Conditions When the bus is not in use, both SCL and SDA must be high. A bus master signals the beginning of a communica- tion to a slave device by transmitting a START condition. A START condition is generated by transitioning SDA from high to low while SCL is high. Table 1 COMMAND* C3 C2 C1 C0 0 0 0 0 Write to Input Register n 0 0 0 1 Update (Power Up) DAC Register n 0 0 1 0 Write to Input Register n, Update (Power Up) All n 0 0 1 1 Write to and Update (Power Up) n 0 1 0 0 Power Down n 1 1 1 1 No Operation *Address and command codes not shown are reserved and should not be used. ADDRESS (n)* A3 A2 A1 A0 0 0 0 0 DAC A 0 0 0 1 DAC B 0 0 1 0 DAC C 0 0 1 1 DAC D 0 1 0 0 DAC E 0 1 0 1 DAC F 0 1 1 0 DAC G 0 1 1 1 DAC H 1 1 1 1 All DACs |
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