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MAX6948B Datasheet(PDF) 5 Page - Maxim Integrated Products |
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MAX6948B Datasheet(HTML) 5 Page - Maxim Integrated Products |
5 / 28 page High-Efficiency PWM LED Driver with Boost Converter and Five Constant-Current GPIO Ports 5 TIMING CHARACTERISTICS (Typical Application Circuit, V+ = 2.7V to 5.0V, VDD = 1.7V to V+, TA = TMIN to TMAX, unless otherwise noted. Typical values are at V+ = 3.3V, VDD = 2.5V, TA = +25NC.) (Note 4) Note 4: All parameters are tested at TA = +25NC. Specifications over temperature are guaranteed by design. Note 5: The DIPORT_ specifies current matching between ports of a single part. Note 6: Current matching is defined as the percent error of any individual port from the average current of the maximum value measured and the minimum value measured. It can be found using the equation DIPORT_ = 100 x (IMMAVG - IMEAS)/ IMMAVG where IMMAVG = (IMEASMAX + IMEASMIN)/2. Note 7: Guaranteed by design. Note 8: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge the undefined region of SCL’s falling edge. Note 9: ISINK P 6mA. Cb = total capacitance of one bus line in pF. tR and tF are measured between 0.3 x VDD and 0.7 x VDD. Note 10: Input filters on the SDA, SCL, and AD0 inputs suppress noise spikes less than 50ns. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Internal Boost-Converter PWM Clock Frequency fINT_ BOOST 98 125 145 kHz Internal GPIO PWM Clock Frequency fINT_GPIO 24 31.25 38 kHz SCL Serial-Clock Frequency fSCL 400 kHz Bus Free Time Between a STOP and START Condition tBUF 1.3 F s Hold Time (Repeated) START Condition tHD, STA 0.6 F s Repeated START Condition Setup Time tSU, STA 0.6 F s STOP Condition Setup Time tSU, STO 0.6 F s Data Hold Time tHD, DAT (Note 8) 0.9 F s Data Setup Time tSU, DAT 180 ns SCL Clock Low Period tLOW 1.3 F s SCL Clock High Period tHIGH 0.7 F s Rise Time of Both SDA and SCL Signals, Receiving tR (Notes 7, 9) 20 + 0.1Cb 300 ns Fall Time of Both SDA and SCL Signals, Receiving tF (Notes 7, 9) 20 + 0.1Cb 300 ns Fall Time of SDA Transmitting tF, TX (Notes 7, 9) 20 + 0.1Cb 250 ns Pulse Width of Spike Suppressed tSP (Notes 7, 10) 50 ns Serial Bus Timeout tOUT 20 30 50 ms Capacitive Load for Each Bus Line Cb (Note 7) 400 pF RST Pulse Width tW 1 F s |
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