1

2

3

4

VSS

VLDO

TDI

SDI

12

11

10

9

16

V2

TMD

TCK

SDO

15

14

13

5

6

7

8

P0019-06

Thermal

Pad

RGTPackage

(TopView)

bq76PL102

Figure 3. bq76PL102 Pinout (Top View)

CAUTION:

This device is subject to damage from Electrostatic Discharge (ESD). The

device should be stored and handled using appropriate ESD precautions to

prevent damage to the internal circuitry.

PIN FUNCTIONS

PIN

NAME

NO.

PUMP1N

6

O

Charge-balance gate drive for cell 1 north

PUMP1S

5

O

Charge-balance gate drive for cell 1 south

PUMP2N

8

O

Charge-balance gate drive cell 2 north

PUMP2S

7

O

Charge-balance gate drive cell 2 south

SDI

4

I

PowerLAN serial data input from lower south, downstream part

SDO

9

O

PowerLAN serial data output to north, upstream part

XT1

14

IA

External temperature sensor 1 input (calibrated 50

µA)

XT2

13

IA

External temperature sensor 2 input (calibrated 50

µA)

TCK

10

NC

Do not connect

TDI

3

NC

Do not connect

TMD

11

NC

Do not connect

V1

15

IA

Midpoint cell connection (cell 1 positive and cell 2 negative)

V2

12

P, IA

VLDO

2

P

Low-dropout regulator output – connect to VPP (bypass with 4.7

µF capacitor)

VPP

16

P

Connect to VLDO

VSS

1

P

Connect to most-negative cell voltage (cell 1 negative)

—

P

Thermal pad – connect to VSS

(1)

I - input, IA - analog input, O - output, P - power, NC - no connect

(2)

Cell numbering convention is from more-negative (cell 1) to more-positive (cell 2) and is locally referenced.

(3)

When there is an odd number of series cells in a battery pack, connect pin V2 of the topmost bq76PL102 to pin V1 of the same

bq76PL102.

4

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