bq24747

Table 1. TERMINAL FUNCTIONS – 28-PIN QFN

TERMINAL

FUNCTION

NO.

1

ICREF

Input current comparator voltage reference input. Connect a resistor-divider from VREF to ICREF, and GND to

program the reference for the ICOUT comparator. The ICREF pin voltage is compared to the VICM pin voltage and

the logic output is given on the ICOUT open-drain pin. Connecting a positive feedback resistor from the ICREF pin to

the ICOUT pin programs the hysteresis.

2

ACIN

Adapter detected voltage set input. Program the adapter detect threshold by connecting a resistor divider from adapter

input to ACIN pin to GND pin. Adapter voltage is detected if ACIN pin voltage is greater than 2.4 V. VICM current

sense amplifier, ICOUT comparator, ICREF input, and ACOK output are active when ACIN pin voltage is greater than

0.6 V.

3

VREF

3.3 V regulated voltage output. Place a 1

μF ceramic capacitor from VREF to GND pin close to the IC. This voltage

could be used for ratio metric programming of voltage and current regulation and for programming the ICREF

threshold.

4

EAO

Error Amplifier Output for compensation. Connect the feedback-compensation components from EAO to EAI.

Typically, a capacitor in parallel with a series resistor and capacitor. This node is internally compared to the PWM

saw-tooth oscillator signal.

5

EAI

Error Amplifier Input for compensation. Connect the feedback compensation components from EAI to EAO. Connect

the input compensation from FBO to EAI.

6

FBO

Feedback Output for compensation. Connect the input compensation from FBO to EAI. Typically, a resistor in parallel

with a series resistor and capacitor.

7

CE

Charge enable active-high logic input. HI enables charge. LO disables charge.

8

VICM

Adapter current sense amplifier output. VICM voltage is 20 times the differential voltage across CSSP-CSSN. Place a

100pF (max) or less ceramic decoupling capacitor from VICM to GND.

9

SDA

SMBus Data input. Connect to SMBus data line from the host controller. A 10-k

Ω pull-up resistor to the host controller

power rail is needed.

10

SCL

SMBus Clock input. Connect to SMBus clock line from the host controller. A 10-k

Ω pull-up resistor to the host

controller power rail is needed.

11

VDDSMB

Input voltage for SMBus logic. Connect a 3.3 V always supply rail, or 5 V always rail to VDDSMB pin. Connect a 0.1

μF

ceramic capacitor from VDDSMB to GND for decoupling.

12

GND

Analog Ground. On PCB layout, connect to the analog ground plane, and only connect to PGND through the

power-pad underneath the IC.

13

ACOK

Valid adapter active-high detect logic open-drain output. Pulled HI when Input voltage is above ACIN programmed

threshold. Connect a 10-k

Ω pull-up resistor from ACOK pin to pull-up supply rail.

14

NC

No Connect. Pin floating internally.

15

VFB

Battery-voltage remote sense. Directly connect a Kelvin sense trace from the battery-pack positive terminal to the VFB

pin to accurately sense the battery pack voltage. Place a 0.1-

μF capacitor from VFB to GND close to the IC to filter

high-frequency noise.

16

NC

No Connect. Pin floating internally.

17

CSON

Charge-current sense resistor, negative input. An optional 0.1-

μF ceramic capacitor is placed from CSON pin to GND

for common-mode filtering. An optional 0.1-

μF ceramic capacitor is placed from CSON to CSOP to provide

differential-mode filtering.

18

CSOP

Charge-current sense resistor, positive input. An optional 0.1-

μF ceramic capacitor is placed from CSOP pin to GND

for common mode filtering. An optional 0.1-

μF ceramic capacitor is placed from CSON to CSOP to provide

differential-mode filtering.

19

PGND

Power ground. On PCB layout, connect directly to source of low-side power MOSFET, to ground connection of input

and output capacitors of the charger. Only connect to GND through the power-pad underneath the IC.

20

LGATE

PWM low-side driver output. Connect to the gate of the low-side power MOSFET with a short trace.

21

VDDP

PWM low-side driver positive 6-V supply output. Connect a 1-

μF ceramic capacitor from VDDP to PGND pin, close to

the IC. Use for high-side driver bootstrap voltage by connecting a small signal Schottky diode from VDDP to BOOT.

22

DCIN

IC-power positive supply. Connect to the common-source (diode-OR) point: source of high-side P-channel MOSFET

and source of reverse blocking power P-channel MOSFET. Place a 1

μF ceramic capacitor from DCIN to PGND pin

close to the IC.

23

PHASE

PWM high-side driver negative supply. Connect to the phase switching node (junction of the low-side power MOSFET

drain, high-side power MOSFET source, and output inductor). Connect the 0.1

μF bootstrap capacitor from PHASE to

BOOT.

24

UGATE

PWM high-side driver output. Connect to the gate of the high-side power MOSFET with a short trace.

25

BOOT

PWM high-side driver positive supply. Connect a 0.1

μF bootstrap ceramic capacitor from BOOT to PHASE. Connect a

small bootstrap Schottky diode from VDDP to BOOT.

4

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