I

RESET TIMING REQUIREMENTS

TCA8418

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 13)

STANDARD MODE

FAST MODE

FAST MODE PLUS (FM+)

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

0

100

0

400

0

1000

kHz

4

0.6

0.26

µs

4.7

1.3

0.5

µs

50

50

50

ns

250

100

50

ns

0

0

0

ns

1000

(1)

300

120

ns

300

(1)

300

120

ns

300

(1)

300

120

µs

4.7

1.3

0.5

µs

Start

4.7

0.6

0.26

µs

setup time

4

0.6

0.26

µs

time

4

0.6

0.26

µs

Valid data time; SCL low to SDA output

1

0.9

0.45

µs

valid

Valid data time of ACK condition; ACK

1

0.9

0.45

µs

signal from SCL low to SDA (out) low

(1)

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 16)

STANDARD MODE, FAST

MODE, FAST MODE PLUS

(FM+)

UNIT

MIN

MAX

Reset pulse duration

µs

Reset recovery time

µs

Time to reset

µs

(1)

The GPIO debounce circuit uses each GPIO input which passes through a two-stage register circuit. Both registers are clocked by the

same clock signal, presumably free-running, with a nominal period of 50uS. When an input changes state, the new state is clocked into

the first stage on one clock transition. On the next same-direction transition, if the input state is still the same as the previously clocked

state, the signal is clocked into the second stage, and then on to the remaining circuits. Since the inputs are asynchronous to the clock,

it will take anywhere from zero to 50

µsec after the input transition to clock the signal into the first stage. Therefore, the total debounce

time may be as long as 100

µsec. Finally, to account for a slow clock, the spec further guard-banded at 120 µsec.

6

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