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TPS54226PW Datasheet(PDF) 5 Page - Texas Instruments |
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TPS54226PW Datasheet(HTML) 5 Page - Texas Instruments |
5 / 21 page SW VBST EN VO VFB GND PGND VO 4 6 9 10 11 1 2 7 12 VIN SS VIN VREG5 EN Logic SW PGND UV OV Protection Logic Ref SS UV OV UVLO UVLO Softstart SS REF TSD Ref VREG5 5 PG 14 13 8 VCC Ceramic Capacitor 3 SGND SGND PGND VCC +20% -10% Ref SW PGND ZC -20% VREG5 VREG5 TPS54226 www.ti.com SLVSA14A – OCTOBER 2009 – REVISED OCTOBER 2009 PIN FUNCTIONS (continued) PIN DESCRIPTION NAME NO. SS 4 Soft-start control. A external capacitor should be connected to GND. GND 5 Signal ground pin PG 6 Open drain power good output EN 7 Enable control input Ground returns for low-side MOSFET. Also serve as inputs of current comparators. Connect PGND and PGND1, PGND2 8, 9 GND strongly together near the IC. Switch node connection between high-side NFET and low-side NFET. Also serve as inputs to current SW1, SW2 10, 11 comparators. Supply input for high-side NFET gate driver (boost terminal). Connect capacitor from this pin to VBST 12 respective SW1, SW2 terminals. An internal PN diode is connected between VREG5 to VBST pin. VIN 13 Power input and connected to high side NFET drain VCC 14 Supply input for 5 V internal linear regulator for the control circuitry Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Should be connected PowerPAD™ Back side to PGND. FUNCTIONAL BLOCK DIAGRAM Copyright © 2009, Texas Instruments Incorporated 5 Product Folder Link(s): TPS54226 |
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