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LAN9303i Datasheet(PDF) 8 Page - SMSC Corporation |
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LAN9303i Datasheet(HTML) 8 Page - SMSC Corporation |
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8 / 366 page  Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII Datasheet Revision 1.3 (08-27-09) 8 SMSC LAN9303/LAN9303i DATASHEET 13.4.2.20 Port x MAC Receive Good Packet Length Count Register (MAC_RX_GOODPKTLEN_CNT_x) ................................................................ 246 13.4.2.21 Port x MAC Receive Symbol Error Count Register (MAC_RX_SYMBOL_CNT_x) ...................................................................................... 247 13.4.2.22 Port x MAC Receive Control Frame Count Register (MAC_RX_CTLFRM_CNT_x) .................................................................................... 248 13.4.2.23 Port x MAC Transmit Configuration Register (MAC_TX_CFG_x) ................................................................................................................ 249 13.4.2.24 Port x MAC Transmit Flow Control Settings Register (MAC_TX_FC_SETTINGS_x) .................................................................................. 250 13.4.2.25 Port x MAC Transmit Deferred Count Register (MAC_TX_DEFER_CNT_x) ............................................................................................... 251 13.4.2.26 Port x MAC Transmit Pause Count Register (MAC_TX_PAUSE_CNT_x) ................................................................................................... 252 13.4.2.27 Port x MAC Transmit OK Count Register (MAC_TX_PKTOK_CNT_x) ........................................................................................................ 253 13.4.2.28 Port x MAC Transmit 64 Byte Count Register (MAC_TX_64_CNT_x) ......................................................................................................... 254 13.4.2.29 Port x MAC Transmit 65 to 127 Byte Count Register (MAC_TX_65_TO_127_CNT_x) ............................................................................... 255 13.4.2.30 Port x MAC Transmit 128 to 255 Byte Count Register (MAC_TX_128_TO_255_CNT_x) ........................................................................... 256 13.4.2.31 Port x MAC Transmit 256 to 511 Byte Count Register (MAC_TX_256_TO_511_CNT_x) ........................................................................... 257 13.4.2.32 Port x MAC Transmit 512 to 1023 Byte Count Register (MAC_TX_512_TO_1023_CNT_x) ....................................................................... 258 13.4.2.33 Port x MAC Transmit 1024 to Max Byte Count Register (MAC_TX_1024_TO_MAX_CNT_x)..................................................................... 259 13.4.2.34 Port x MAC Transmit Undersize Count Register (MAC_TX_UNDSZE_CNT_x) .......................................................................................... 260 13.4.2.35 Port x MAC Transmit Packet Length Count Register (MAC_TX_PKTLEN_CNT_x) .................................................................................... 261 13.4.2.36 Port x MAC Transmit Broadcast Count Register (MAC_TX_BRDCST_CNT_x) .......................................................................................... 262 13.4.2.37 Port x MAC Transmit Multicast Count Register (MAC_TX_MULCST_CNT_x) ............................................................................................ 263 13.4.2.38 Port x MAC Transmit Late Collision Count Register (MAC_TX_LATECOL_CNT_x) ................................................................................... 264 13.4.2.39 Port x MAC Transmit Excessive Collision Count Register (MAC_TX_EXCCOL_CNT_x)............................................................................ 265 13.4.2.40 Port x MAC Transmit Single Collision Count Register (MAC_TX_SNGLECOL_CNT_x) ............................................................................. 266 13.4.2.41 Port x MAC Transmit Multiple Collision Count Register (MAC_TX_MULTICOL_CNT_x) ............................................................................ 267 13.4.2.42 Port x MAC Transmit Total Collision Count Register (MAC_TX_TOTALCOL_CNT_x)................................................................................ 268 13.4.2.43 Port x MAC Interrupt Mask Register (MAC_IMR_x) ..................................................................................................................................... 269 13.4.2.44 Port x MAC Interrupt Pending Register (MAC_IPR_x) ................................................................................................................................. 270 13.4.3 Switch Engine CSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 13.4.3.1 Switch Engine ALR Command Register (SWE_ALR_CMD) ........................................................................................................................ 271 13.4.3.2 Switch Engine ALR Write Data 0 Register (SWE_ALR_WR_DAT_0) .......................................................................................................... 272 13.4.3.3 Switch Engine ALR Write Data 1 Register (SWE_ALR_WR_DAT_1) .......................................................................................................... 273 13.4.3.4 Switch Engine ALR Read Data 0 Register (SWE_ALR_RD_DAT_0)........................................................................................................... 275 13.4.3.5 Switch Engine ALR Read Data 1 Register (SWE_ALR_RD_DAT_1)........................................................................................................... 276 13.4.3.6 Switch Engine ALR Command Status Register (SWE_ALR_CMD_STS) .................................................................................................... 278 13.4.3.7 Switch Engine ALR Configuration Register (SWE_ALR_CFG) .................................................................................................................... 279 13.4.3.8 Switch Engine VLAN Command Register (SWE_VLAN_CMD).................................................................................................................... 280 13.4.3.9 Switch Engine VLAN Write Data Register (SWE_VLAN_WR_DATA).......................................................................................................... 281 13.4.3.10 Switch Engine VLAN Read Data Register (SWE_VLAN_RD_DATA) .......................................................................................................... 283 13.4.3.11 Switch Engine VLAN Command Status Register (SWE_VLAN_CMD_STS) ............................................................................................... 284 13.4.3.12 Switch Engine DIFFSERV Table Command Register (SWE_DIFFSERV_TBL_CFG)................................................................................. 285 13.4.3.13 Switch Engine DIFFSERV Table Write Data Register (SWE_DIFFSERV_TBL_WR_DATA) ...................................................................... 286 13.4.3.14 Switch Engine DIFFSERV Table Read Data Register (SWE_DIFFSERV_TBL_RD_DATA) ....................................................................... 287 13.4.3.15 Switch Engine DIFFSERV Table Command Status Register (SWE_DIFFSERV_TBL_CMD_STS) ............................................................ 288 13.4.3.16 Switch Engine Global Ingress Configuration Register (SWE_GLOBAL_INGRSS_CFG)............................................................................. 289 13.4.3.17 Switch Engine Port Ingress Configuration Register (SWE_PORT_INGRSS_CFG) ..................................................................................... 291 13.4.3.18 Switch Engine Admit Only VLAN Register (SWE_ADMT_ONLY_VLAN)..................................................................................................... 292 13.4.3.19 Switch Engine Port State Register (SWE_PORT_STATE)........................................................................................................................... 293 13.4.3.20 Switch Engine Priority to Queue Register (SWE_PRI_TO_QUE) ................................................................................................................ 294 13.4.3.21 Switch Engine Port Mirroring Register (SWE_PORT_MIRROR).................................................................................................................. 295 13.4.3.22 Switch Engine Ingress Port Type Register (SWE_INGRSS_PORT_TYP) ................................................................................................... 296 13.4.3.23 Switch Engine Broadcast Throttling Register (SWE_BCST_THROT) .......................................................................................................... 297 13.4.3.24 Switch Engine Admit Non Member Register (SWE_ADMT_N_MEMBER)................................................................................................... 298 13.4.3.25 Switch Engine Ingress Rate Configuration Register (SWE_INGRSS_RATE_CFG) .................................................................................... 299 13.4.3.26 Switch Engine Ingress Rate Command Register (SWE_INGRSS_RATE_CMD)......................................................................................... 300 13.4.3.26.1Ingress Rate Table Registers.................................................................................................301 13.4.3.27 Switch Engine Ingress Rate Command Status Register (SWE_INGRSS_RATE_CMD_STS) .................................................................... 302 13.4.3.28 Switch Engine Ingress Rate Write Data Register (SWE_INGRSS_RATE_WR_DATA)............................................................................... 303 13.4.3.29 Switch Engine Ingress Rate Read Data Register (SWE_INGRSS_RATE_RD_DATA) ............................................................................... 304 13.4.3.30 Switch Engine Port 0 Ingress Filtered Count Register (SWE_FILTERED_CNT_0) ..................................................................................... 305 13.4.3.31 Switch Engine Port 1 Ingress Filtered Count Register (SWE_FILTERED_CNT_1) ..................................................................................... 306 13.4.3.32 Switch Engine Port 2 Ingress Filtered Count Register (SWE_FILTERED_CNT_2) ..................................................................................... 307 13.4.3.33 Switch Engine Port 0 Ingress VLAN Priority Regeneration Table Register (SWE_INGRSS_REGEN_TBL_0) ........................................... 308 13.4.3.34 Switch Engine Port 1 Ingress VLAN Priority Regeneration Table Register (SWE_INGRSS_REGEN_TBL_1) ........................................... 309 13.4.3.35 Switch Engine Port 2 Ingress VLAN Priority Regeneration Table Register (SWE_INGRSS_REGEN_TBL_2) ........................................... 310 13.4.3.36 Switch Engine Port 0 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_0) .................................................................................. 311 13.4.3.37 Switch Engine Port 1 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_1) .................................................................................. 312 13.4.3.38 Switch Engine Port 2 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_2) .................................................................................. 313 13.4.3.39 Switch Engine Interrupt Mask Register (SWE_IMR)..................................................................................................................................... 314 13.4.3.40 Switch Engine Interrupt Pending Register (SWE_IPR)................................................................................................................................. 315 13.4.4 Buffer Manager CSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 13.4.4.1 Buffer Manager Configuration Register (BM_CFG) ...................................................................................................................................... 317 13.4.4.2 Buffer Manager Drop Level Register (BM_DROP_LVL)............................................................................................................................... 318 13.4.4.3 Buffer Manager Flow Control Pause Level Register (BM_FC_PAUSE_LVL)............................................................................................... 319 13.4.4.4 Buffer Manager Flow Control Resume Level Register (BM_FC_RESUME_LVL) ........................................................................................ 320 13.4.4.5 Buffer Manager Broadcast Buffer Level Register (BM_BCST_LVL)............................................................................................................. 321 13.4.4.6 Buffer Manager Port 0 Drop Count Register (BM_DRP_CNT_SRC_0) ....................................................................................................... 322 13.4.4.7 Buffer Manager Port 1 Drop Count Register (BM_DRP_CNT_SRC_1) ....................................................................................................... 323 13.4.4.8 Buffer Manager Port 2 Drop Count Register (BM_DRP_CNT_SRC_2) ....................................................................................................... 324 13.4.4.9 Buffer Manager Reset Status Register (BM_RST_STS) .............................................................................................................................. 325 13.4.4.10 Buffer Manager Random Discard Table Command Register (BM_RNDM_DSCRD_TBL_CMD) ................................................................ 326 13.4.4.11 Buffer Manager Random Discard Table Write Data Register (BM_RNDM_DSCRD_TBL_WDATA) ........................................................... 327 13.4.4.12 Buffer Manager Random Discard Table Read Data Register (BM_RNDM_DSCRD_TBL_RDATA)............................................................ 328 13.4.4.13 Buffer Manager Egress Port Type Register (BM_EGRSS_PORT_TYPE) ................................................................................................... 329 |
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