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December 5, 2008

IDT79R4700

Pin Description

The table below provides a list of interface, interrupt and miscellaneous pins that are available on the RC4700. Note that signals marked with an

asterisk are active when low. Boundary scan is not supported.

Pin Name Type

Description

System Interface

ExtRqst*

I

External request

Signals that the system interface needs to submit an external request.

Release*

O

Release interface

Signals that the processor is releasing the system interface to slave state.

RdRdy*

I

Read Ready

Signals that an external agent can now accept a processor read.

WrRdy*

I

Write Ready

Signals that an external agent can now accept a processor write request.

ValidIn*

I

Valid Input

Signals that an external agent is now driving a valid address or data on the SysAD bus and a valid com-

mand or data identifier on the SysCmd bus.

ValidOut*

O

Valid output

Signals that the processor is now driving a valid address or data on the SysAD bus and a valid command or

data identifier on the SysCmd bus.

SysAD(63:0)

I/O

System address/data bus

A 64-bit address and data bus for communication between the processor and an external agent.

SysADC(7:0)

I/O

System address/data check bus

An 8-bit bus containing parity check bits for the SysAD bus during data bus cycles.

SysCmd(8:0)

I/O

System command/data identifier bus

A 9-bit bus for command and data identifier transmission between the processor and an external agent.

SysCmdP

I/O

Reserved system command/data identifier bus parity

for the R4700 unused on input and zero on output.

Clock/Control Interface

MasterClock

I

Master clock

Master clock input at one half the processor operating frequency.

MasterOut

O

Master clock out

Master clock output aligned with MasterClock.

RClock(1:0)

O

Receive clocks

Two identical receive clocks at the system interface frequency.

TClock(1:0)

O

Transmit clocks

Two identical transmit clocks at the system interface frequency.

IOOut

O

Reserved for future output

Always HIGH.

IOIn

I

Reserved for future input

Should be driven HIGH.

SyncOut

O

Synchronization clock out

Must be connected to SyncIn through an interconnect that models the interconnect between MasterOut,

TClock, RClock, and the external agent.

SyncIn

I

Synchronization clock in

Synchronization clock input. See SyncOut.

Fault*

O

Fault

Always HIGH.