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79RV4700-133GH Datasheet(PDF) 1 Page - Integrated Device Technology |
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79RV4700-133GH Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 25 page 1 of 25 December 5, 2008 © 2008 Integrated Device Technology, Inc. DSC 9096 64-Bit RISC Microprocessor Features ◆ True 64-bit microprocessor – 64-bit integer operations – 64-bit floating-point operations – 64-bit registers – 64-bit virtual address space ◆ High-performance microprocessor – 260 Dhrystone MIPS at 200MHz – 100 peak MFLOP/s at 200MHz – Two-way set associative caches – Simple 5-stage pipeline ◆ High level of integration – 64-bit, 200 MHz integer CPU – 64-bit floating-point unit – 16KB instruction cache – 16KB data cache – Flexible MMU with large, fully associative TLB ◆ Low-power operation – 3.3V power supply, for the “RV” part – 5V power supply, for the “R” part – Dynamic power management – Standby mode reduces internal power ◆ Fully software & pin-compatible with 40XX Processor Family ◆ Available in 179-pin PGA or 208-pin QFP ◆ Available at 80-200MHz, with mode bit dependent output clock frequencies ◆ 64GB physical address space ◆ Processor family for a wide variety of embedded applications – LAN switches – Routers – Color printers Description The IDT79R4700 64-bit RISC Microprocessor is both software and pin-compatible with the R4XXX processor family. With 64-bit processing capabilities, the R4700 provides more computational power and data movement bandwidth than is delivered to typical embedded systems by 32-bit processors. The R4700 is upwardly software compatible with the IDT79R3000™ microprocessor family, including the IDTRISController™ 79R3051™, R3052™, R3041™, R3081™ as well as the R4640™, R4650™, RC64474/ 475™ and R5000™. An array of development tools facilitates rapid development of R4700-based systems, allowing a variety of customers access to the MIPS Open Architecture philosophy. Block Diagram The IDT logo is a trademark and RC32134, RC32364, RC64145, RC64474, RC64475, RC4650, RC4640, RC4600,RC4700 RC3081, RC3052, RC3051, RC3041, RISController, and RISCore are trademarks of Inte- grated Device Technology, Inc. Read Buffer Integer Register File Integer/Address Adder Data TLB Virtual Shifter/Store Aligner Logic Unit Program Counter PC Incrementer Branch Adder Load Aligner Floating-point Unpacker/Packer Floating-point Add/Sub/Cvt/Div/Sqrt Integer Divide Floating-point/Integer Phase Lock Loop, Clocks Instruction TLB Virtual Joint TLB Data Set A Data Set B Data Tag A DTLB Physical Address Buffer Data Tag B Instruction Tag A Instruction Tag B ITLB Physical Store Buffer Write Buffer DVA IVA Instruction Set A Instruction Set B Multiply SysAD IBus DBus Coprocessor 0 System/Memory Control Tag AuxTag Instruction Select Control Instruction Register Register File IDT79R4700 |
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