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79R4640-200DUGI Datasheet(PDF) 3 Page - Integrated Device Technology |
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79R4640-200DUGI Datasheet(HTML) 3 Page - Integrated Device Technology |
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3 / 23 page  3 of 23 December 5, 2008 IDT79RC4640™ The MIPS-III architecture defines that the results of a multiply or divide operation are placed in the HI and LO registers. The values can then be transferred to the general purpose register file using the MFHI/ MFLO instructions. The RC4640 adds a new multiply instruction, “MUL”, which can specify that the multiply results bypass the “Lo” register and are placed immediately in the primary register file. By avoiding the explicit “Move- from-Lo” instruction required when using “Lo”, throughput of multiply- intensive operations is increased. An additional enhancement offered by the RC4640 is an atomic “multiply-add” operation, MAD, used to perform multiply-accumulate operations. This instruction multiplies two numbers and adds the product to the current contents of the HI and LO registers. This operation is used in numerous DSP algorithms, and allows the RC4640 to cost reduce systems requiring a mix of DSP and control functions. Finally, aggressive implementation techniques feature low latency for these operations along with pipelining to allow new operations to be issued before a previous one has fully completed. Table 1 also shows the repeat rate (peak issue rate), latency, and number of processor stalls required for the various operations. The RC4640 performs automatic operand size detection to determine the size of the operand, and imple- ments hardware interlocks to prevent overrun, allowing this high-perfor- mance to be achieved with simple programming. Floating-Point Coprocessor The RC4640 incorporates an entire single-precision floating-point coprocessor on chip, including a floating-point register file and execution units. The floating-point coprocessor forms a “seamless” interface with the integer unit, decoding and executing instructions in parallel with the integer unit. The floating-point unit of the RC4640 directly implements single- precision floating-point operations, which enables the RC4640 to perform functions such as graphics rendering without requiring exten- sive die area or power consumption. The single-precision unit of the RC4640 is directly compatible with the single-precision operation of the RC4700, and features the same latencies and repeat rates. The RC4640 does not directly implement the double-precision opera- tions found in the RC4700. However, to maintain software compatibility, the RC4640 will signal a trap when a double-precision operation is initi- ated, allowing the requested function to be emulated in software. Alter- natively, the system architect could use a software library emulation of double-precision functions, selected at compile time, to eliminate the overhead associated with trap and emulation. Floating-Point Units The RC4640’s floating-point execution units perform single precision arithmetic, as specified in IEEE Standard 754. The execution unit is broken into a separate multiply unit and a combined add/convert/divide/ square root unit. Overlap of multiply and add/subtract is supported. The multiplier is partially pipelined, allowing a new multiplication instruction to begin every 6 cycles. As in the IDT79RC4700, the RC4640 maintains fully precise floating- point exceptions while allowing both overlapped and pipelined opera- tions. Precise exceptions are extremely important in mission-critical environments, such as ADA, and highly desirable for debugging in any environment. The floating-point unit’s operation set includes floating-point add, subtract, multiply, divide, square root, conversion between fixed-point and floating-point format, conversion among floating-point formats, and floating-point compare. These operations comply with IEEE Standard 754. Double precision operations are not directly supported; attempts to execute double-precision floating point operations, or refer directly to double-precision registers, result in the RC4640 signalling a “trap” to the CPU, enabling emulation of the requested function. Table 2 gives the latencies of some of the floating-point instructions in internal processor cycles. Floating-Point General Register File The floating-point register file is made up of thirty-two 32-bit regis- ters. These registers are used as source or target registers for the single-precision operations. References to these registers as 64-bit registers (as supported in the RC4700) will cause a trap to be signalled to the integer unit. The floating-point control register space contains two registers; one for determining configuration and revision information for the copro- cessor and one for control and status information. These are primarily involved with diagnostic software, exception handling, state saving and restoring, and control of rounding modes. Operation Instruction Latency ADD 4 SUB 4 MUL 8 DIV 32 SQRT 31 CMP 3 FIX 4 FLOAT 6 ABS 1 MOV 1 NEG 1 LWC1 2 SWC1 1 Table 2 Floating-Point Operation |
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