MXED401

14580

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6

FIGURE 5 - TYPICAL PIN VOLTAGE WAVEFORMS

HREF Bias Generator

The output stage requires a reference supply 3.8 to 4.2 volts lower than PV4 into each HIN input.

This may be provided by the system designer or generated on-chip. When HEN is held high, a bias

voltage is generated at the HREF output which is (PV4-4.0v). This generated voltage may then be

used to supply 6 HIN inputs. The HREF output must be stabilized by connecting a 0.1uF capacitor

between HREF and PV4. A separate stabilizing capacitor is required for each HREF used. It is

forbidden to connect any HREF pin to another HREF pin. Each enabled HREF output causes an

additional DC current of 60uA (130 uA maximum) to flow from PV4 to MV4.