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IKCS12F60AC Datasheet(PDF) 6 Page - Infineon Technologies AG |
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IKCS12F60AC Datasheet(HTML) 6 Page - Infineon Technologies AG |
6 / 19 page CIPOS™ IKCS12F60AA IKCS12F60AC Data Sheet 6/19 Rev. 2.2, Nov. 2008 Pin Assignment Pin Number Pin Name Pin Description 1 VB3 high side floating IC supply voltage 2 W,VS3 motor output W, high side floating IC supply offset voltage 3 n.a. None 4 VB2 high side floating IC supply voltage 5 V,VS2 motor output V, high side floating IC supply offset voltage 6 n.a. None 7 VB1 high side floating IC supply voltage 8 U,VS1 motor output U, high side floating IC supply offset voltage 9 n.a. None 10 V+ positive bus input voltage 11 n.a. None 12 VRU low side emitter 13 VRV low side emitter 14 VRW low side emitter 15 /HIN1 input gate driver high side 1/U 16 /HIN2 input gate driver high side 2/V 17 /HIN3 input gate driver high side 3/W 18 /LIN1 input gate driver low side 1/U 19 /LIN2 input gate driver low side 2/V 20 /LIN3 input gate driver low side 3/W 21 ITRIP input overcurrent shutdown 22 VDD module control supply 23 VSS module negative supply 24 EN input logic enable, output temperature monitoring Pin Description /HIN1,2,3 and /LIN1,2,3 (Low side and high side control pins, Pin 15 - 20) These pins are active low and they are responsible for the control of the integrated IGBT The Schmitt-trigger input threshold of them are such to guarantee LSTTL and CMOS compatibility down to 3.3V controller outputs. Pull-up resistor of about 75 kOhm is internally provided to pre-bias inputs during supply start-up and a zener clamp is provided for pin protection purposes. Input schmitt-trigger and noise filter provide beneficial noise rejection to short input pulses. It is recommended for proper work of CiPoS™ not to provide input pulse-width lower than 1us. The integrated gate drive provides additionally a shoot through prevention capability which avoids the simultaneous on-state of two gate drivers of the same leg (i.e. HO1 and LO1, HO2 and LO2, HO3 and LO3). Figure 2: Input pin structure |
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