ICS830S21I

1-TO-1, 2.5V, 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR

IDT™ / ICS™ LVCMOS/LVTTL TRANSLATOR

4

ICS830S21AMI REV. A MARCH 21, 2008

AC Electrical Characteristics

NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input High Current

150

µA

Input Low Current

-150

µA

Peak-to-Peak Voltage; NOTE 1

0.15

1.5

V

Common Mode Input Voltage;

NOTE 1, 2

GND + 0.5

V

Output Voltage Reference

V

Parameter

Symbol

Test Conditions

Minimum

Typical

Maximum

Units

Output Frequency

350

MHz

Propagation Delay, NOTE 1

0.95

1.95

ns

tsk(pp)

Part-to-Part Skew; NOTE 2, 3

525

ps

tjit

Buffer Additive Phase jitter, RMS;

refer to Additive Phase Jitter Section

350MHz, Integration Range

(12kHz – 20MHz)

0.11

1

ps

Output Rise/Fall Time

20% to 80%

85

500

ps

odc

Output Duty Cycle

ƒ

≤ 266MHz

47

53

%

Parameter

Symbol

Test Conditions

Minimum

Typical

Maximum

Units

Output Frequency

350

MHz

Propagation Delay, NOTE 1

1

2

ns

tsk(pp)

Part-to-Part Skew; NOTE 2, 3

550

ps

tjit

Buffer Additive Phase jitter, RMS;

refer to Additive Phase Jitter Section

350MHz, Integration Range

(12kHz – 20MHz)

0.11

1

ps

Output Rise/Fall Time

20% to 80%

125

500

ps

odc

Output Duty Cycle

ƒ

≤ 266MHz

47

53

%