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ICS840S06I Datasheet(PDF) 10 Page - Integrated Device Technology |
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ICS840S06I Datasheet(HTML) 10 Page - Integrated Device Technology |
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10 / 20 page  ICS840S06I CLOCK GENERATOR FOR CAVIUM PROCESSORS PRELIMINARY IDT™ / ICS™ CLOCK GENERATOR 10 ICS840S06AKI REV. AI JULY 10, 2008 Application Information Wiring the Differential Input to Accept Single-Ended Levels Figure 1 shows how the differential input can be wired to accept single-ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. Figure 1. Single-Ended Signal Driving Differential Input Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter per- formance, power supply isolation is required. The ICS840S06I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO_X should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 2 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10Ω resistor along with a 10 µF bypass capacitor be connected to the V DDA pin. Figure 2. Power Supply Filtering V_REF Single Ended Clock Input VDD CLK nCLK R1 1K C1 0.1u R2 1K VDD VDDA 3.3V 10 Ω 10µF .01µF .01µF |
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