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ICS1893BFILFT Datasheet(PDF) 4 Page - Integrated Device Technology

Part # ICS1893BFILFT
Description  3.3-V 10Base-T/100Base-TX Integrated PHYceiver?
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

ICS1893BFILFT Datasheet(HTML) 4 Page - Integrated Device Technology

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ICS1893BF, Rev. E, 8/11/09
August, 2009
4
Table of Contents
ICS1893BF Data Sheet - Release
Copyright © 2009, IDT, Inc.
All rights reserved.
Table of Contents
Section
Title
Page
Chapter 7
Management Register Set ............................................................................................... 49
7.1
Introduction to Management Register Set .............................................................50
7.1.1
Management Register Set Outline .........................................................................50
7.1.2
Management Register Bit Access ..........................................................................51
7.1.3
Management Register Bit Default Values ..............................................................51
7.1.4
Management Register Bit Special Functions .........................................................52
7.2
Register 0: Control Register ...................................................................................53
7.2.1
Reset (bit 0.15) ......................................................................................................53
7.2.2
Loopback Enable (bit 0.14) ....................................................................................54
7.2.3
Data Rate Select (bit 0.13) .....................................................................................54
7.2.4
Auto-Negotiation Enable (bit 0.12) .........................................................................54
7.2.5
Low Power Mode (bit 0.11) ....................................................................................55
7.2.6
Isolate (bit 0.10) .....................................................................................................55
7.2.7
Restart Auto-Negotiation (bit 0.9) ..........................................................................55
7.2.8
Duplex Mode (bit 0.8) .............................................................................................56
7.2.9
Collision Test (bit 0.7) ............................................................................................56
7.2.10
IEEE Reserved Bits (bits 0.6:0) .............................................................................56
7.3
Register 1: Status Register ....................................................................................57
7.3.1
100Base-T4 (bit 1.15) ............................................................................................57
7.3.2
100Base-TX Full Duplex (bit 1.14) .........................................................................58
7.3.3
100Base-TX Half Duplex (bit 1.13) ........................................................................58
7.3.4
10Base-T Full Duplex (bit 1.12) .............................................................................58
7.3.5
10Base-T Half Duplex (bit 1.11) ............................................................................ 58
7.3.6
IEEE Reserved Bits (bits 1.10:7) ...........................................................................59
7.3.7
MF Preamble Suppression (bit 1.6) .......................................................................59
7.3.8
Auto-Negotiation Complete (bit 1.5) .......................................................................59
7.3.9
Remote Fault (bit 1.4) ............................................................................................60
7.3.10
Auto-Negotiation Ability (bit 1.3) ............................................................................60
7.3.11
Link Status (bit 1.2) ................................................................................................60
7.3.12
Jabber Detect (bit 1.1) ...........................................................................................61
7.3.13
Extended Capability (bit 1.0) ..................................................................................61
7.4
Register 2: PHY Identifier Register ........................................................................62


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