ICS8430-62 Datasheet

500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

ICS8430AY-62 REVISION A JULY 2, 2009

3

©2009 Integrated Device Technology, Inc.

Table 1. Pin Descriptions

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Number

Name

Type

Description

1, 2, 28, 29,

30, 31, 32

M5, M6, M0, M1,

M2, M3, M4

Input

Pulldown

M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input.

LVCMOS/LVTTL interface levels.

3, 4

M7, M8

Input

Pullup

5, 7

N0, N2

Input

Pulldown

Determines output divider value as defined in Table 3C, Function Table.

LVCMOS/LVTTL interface levels.

6

N1

Input

Pullup

8, 16

Power

Negative supply pins.

9

TEST

Output

Test output which is ACTIVE in the serial mode of operation.

Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels.

10

Power

Core supply pin.

11, 12

FOUT1, nFOUT1

Output

Differential output pair for the synthesizer. LVPECL interface levels.

13

Power

Output supply pin for LVPECL outputs.

14, 15

FOUT0, nFOUT0

Output

Differential output pair for the synthesizer. LVPECL interface levels.

17

MR

Input

Pulldown

Active High Master Reset. When logic HIGH, the internal dividers are reset

causing the true outputs FOUTx to go low and the inverted outputs nFOUTx to

go high. When Logic LOW, the internal dividers and the outputs are enabled.

Assertion of MR does not affect loaded M, N, and T values.

LVCMOS/LVTTL interface levels.

18

S_CLOCK

Input

Pulldown

Clocks in serial data present at S_DATA input into the shift register on the

rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.

19

S_DATA

Input

Pulldown

Shift register serial input. Data sampled on the rising edge of S_CLOCK.

LVCMOS/LVTTL interface levels.

20

S_LOAD

Input

Pulldown

Controls transition of data from shift register into the dividers.

LVCMOS/LVTTL interface levels.

21

Power

Analog supply pin.

22

XTAL_SEL

Input

Pullup

Selects between crystal oscillator or REF_CLK inputs as the PLL reference

source. Selects XTAL inputs when HIGH. Selects REF_CLK when LOW.

LVCMOS/LVTTL interface levels.

23

REF_CLK

Input

Pulldown

Single-ended reference clock input. LVCMOS/LVTTL interface levels.

24,

25

XTAL_OUT

XTAL_IN

Input

Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.

26

nP_LOAD

Input

Pulldown

Parallel load input. Determines when data present at M8:M0 is loaded into M

divider, and when data present at N2:N0 sets the N output divider value.

LVCMOS/LVTTL interface levels.

27

VCO_SEL

Input

Pullup

Determines whether synthesizer is in PLL or bypass mode. When LOW,

synthesizer is in bypass mode, when HIGH,synthesizer is in PLL mode.

LVCMOS/LVTTL interface levels.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input Capacitance

4

pF

Input Pullup Resistor

51

k

Ω

Input Pulldown Resistor

51

k

Ω