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ICS8440258AK-46LFT Datasheet(PDF) 10 Page - Integrated Device Technology |
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ICS8440258AK-46LFT Datasheet(HTML) 10 Page - Integrated Device Technology |
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10 / 16 page  IDT™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER 10 ICS8440258AK-46 REV B JANUARY 15, 2008 ICS8440258-46 FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER PRELIMINARY transmission line environment. For buffer with multiple LDVS driver, it is recommended to terminate the unused outputs. 2.5V LVDS DRIVER TERMINATION Figure 4 shows a typical ter mination for LVDS driver in characteristic impedance of 100 Ω differential (50Ω single) FIGURE 4. TYPICAL LVDS DRIVER TERMINATION 2.5V 100 Ohm Differential Transmission Line 2.5V LVDS_Driv er R1 100 + - 100 Ω Ω Ω Ω Ω DifferentialTransmission Line FIGURE 5. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE) VFQFN EPAD THERMAL RELEASE PATH In order to maximize both the removal of heat from the package and the electr ical perfor mance, a land patter n must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 5. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/ slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadfame Base Package, Amkor Technology. THERMAL VIA LAND PATTERN SOLDER PIN SOLDER PIN PAD PIN PAD PIN GROUND PLANE EXPOSED HEAT SLUG (GROUND PAD) |
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