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EM68B32DVKA-6H Datasheet(PDF) 7 Page - Etron Technology, Inc.

Part # EM68B32DVKA-6H
Description  16M x 32 Mobile DDR Synchronous DRAM (SDRAM)
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Manufacturer  ETRON [Etron Technology, Inc.]
Direct Link  http://www.etron.com
Logo ETRON - Etron Technology, Inc.

EM68B32DVKA-6H Datasheet(HTML) 7 Page - Etron Technology, Inc.

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EtronTech
EM68B32DVKA
Etron Confidential
7
Rev. 1.0
Mar. 2009
Mode Register Set(MRS)
The Mode Register stores the data for controlling various operating modes of a DDR SDRAM. It programs
CAS Latency, Burst Type, and Burst Length to make the Mobile DDR SDRAM useful for a variety of
applications. The default value of the Mode Register is not defined; therefore the Mode Register must be
written by the user. Values stored in the register will be retained until the register is reprogrammed, the
device enters Deep Power Down mode, or power is removed from the device. The Mode Register is written
by asserting Low on CS , RAS , CAS , WE , BA1 and BA0 (the device should have all banks idle with no
bursts in progress prior to writing into the mode register, and CKE should be High). The state of address pins
A0~A12 and BA0, BA1 in the same cycle in which CS , RAS , CAS and WE are asserted Low is written into
the Mode Register. A minimum of two clock cycles, tMRD, are required to complete the write operation in the
Mode Register. The Mode Register is divided into various fields depending on functionality. The Burst Length
uses A0~A2, Burst Type uses A3, and CAS Latency (read latency from column address) uses A4~A6. A
logic 0 should be programmed to all the undefined addresses to ensure future compatibility. Reserved states
should not be used to avoid unknown device operation or incompatibility with future versions. Refer to the
table for specific codes for various burst lengths, burst types and CAS latencies.
Table 4. Mode Register Bitmap
BA1 BA0 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Field
0
0
0
0
0
0
CAS
Latency
BT
Burst Length
Mode Register
A6 A5 A4 CAS Latency A3 Burst Type A2 A1 A0
Burst Length
0
0
0
Reserved
0
Sequential
000
Reserved
0
0
1
Reserved
1
Interleave
0
0
1
2
0
1
0
2
0
1
0
4
0
1
1
3
011
8
1
0
0
Reserved
100
16
1
0
1
Reserved
101
Reserved
1
1
0
Reserved
110
Reserved
1
1
1
Reserved
111
Reserved
NOP
PRE
ALL
NOP
tRP
*2
Don’t Care
*1: MRS can be issued only with all banks in the idle state.
*2: A minimum delay of tRP is required before issuing an MRS command.
NOP
MRS
*1
NOP
Any
Command
NOP
NOP
tMRD= 2*tCK
CK
CK
Command
Figure 3.Mode Register Set Cycle


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