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EM68916CWQA-3H Datasheet(PDF) 10 Page - Etron Technology, Inc. |
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EM68916CWQA-3H Datasheet(HTML) 10 Page - Etron Technology, Inc. |
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10 / 59 page  EtronTech EM68916CWQA Etron Confidential 10 Rev. 1.1 Apr. 2009 Extended Mode Register Set (EMRS ) - EMR(1) The extended mode register(1) stores the data for enabling or disabling the DLL, output driver strength, ODT value selection and additive latency. The default value of the extended mode register is not defined, therefore the extended mode register must be written after power-up for proper operation. The extended mode register is written by asserting LOW on CS#, RAS#, CAS#, WE# and HIGH on BA0, while controlling the states of address pins A0 ~ A12. The DDR2 SDRAM should be in all bank precharge with CKE already HIGH prior to writing into the extended mode register. The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register. Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. A0 is used for DLL enable or disable. A1 is used for enabling a half strength data-output driver. A3~A5 determine the additive latency, A2 and A6 are used for ODT value selection, A7~A9 are used for OCD control, A10 is used for DQS# disable. - DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having the DLL disabled. The DLL is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled (and subsequently reset), 200 clock cycles must occur before a Read command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters. Table 6. Extended Mode Resistor EMR (1) Bitmap BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field 0 1 Qoff 0 DQS# OCD program Rtt Additive Latency Rtt D.I.C DLL Extended Mode Register BA1 BA0 MRS mode A6 A2 Rtt(NOMINAL) 0 0 MR 0 0 ODT Disable A0 DLL Enable 0 1 EMR(1) 0 1 75Ω 0 Enable 1 0 EMR(2) 1 0 150Ω 1 Disable 1 1 EMR(3) 1 1 50Ω A9 A8 A7 OCD Calibration Program 0 0 0 OCD Calibration mode exit; maintain setting A1 Output Driver Impedance Control 0 0 1 Drive(1) 0 Full strength 0 1 0 Drive(0) 1 Reduced strength 1 0 0 Adjust mode *1 1 1 1 OCD Calibration default *2 A5 A4 A3 Additive Latency 000 0 A12 Qoff *3 001 1 0 Output buffer enabled 0 1 0 2 A10 DQS# 1 Output buffer disabled 0 1 1 3 0 Enable 1 0 0 4 1 Disable 1 0 1 5 110 Reserved 111 Reserved NOTE 1: When Adjust mode is issued, AL from previously set value must be applied. NOTE 2: After setting to default, OCD calibration mode needs to be exited by setting A9-A7 to 000. NOTE 3: Output disabled – DQs, DQSs, DQSs#.This feature is intended to be used during IDD characterization of read current. |
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