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6T39007ANLGI8 Datasheet(PDF) 7 Page - Integrated Device Technology |
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6T39007ANLGI8 Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 15 page IDT6T39007A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS IDT™ CLOCK DISTRIBUTION CIRCUIT 7 IDT6T39007A REV G 111009 Byte 3: Control Register Byte 4 through 5: Control Register Byte 6: Control Register 2 PWRCTRL_CLK2 Divider SEL bit 2 RW 1 PWRCTRL_CLK1 Default is /46 to get 282.6kHz from 13 MHz 1 PWRCTRL_CLK2 Divider SEL bit 1 RW 1 PWRCTRL_CLK1 Default is /46 to get 282.6kHz from 13 MHz 0 PWRCTRL_CLK2 Divider SEL bit 0 RW 0 PWRCTRL_CLK1 Default is /46 to get 282.6kHz from 13 MHz Bit Description Type Power Up Condition Output(s) Affected Notes 7 to 0 Reserved R Undefined Not applicable Bit Description Type Power Up Condition Output(s) Affected Notes 7 to 0 Reserved R Undefined Not applicable Bit Description Type Power Up Output(s) Affected Notes 7 Revision ID bit 3 R 0 Not applicable 6 Revision ID bit 2 R 0 Not applicable 5 Revision ID bit 1 R 0 Not applicable 4 Revision ID bit 0 R 0 Not applicable 3 Vendor ID bit 3 R 0 Not applicable 2 Vendor ID bit 2 R 0 Not applicable 1 Vendor ID bit 1 R 0 Not applicable 0 Vendor ID bit 0 R 1 Not applicable |
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