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ATF22V10C-15PU Datasheet(PDF) 8 Page - ATMEL Corporation |
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ATF22V10C-15PU Datasheet(HTML) 8 Page - ATMEL Corporation |
8 / 23 page 8 0735T–PLD–5/09 ATF22V10C(Q) 7. Programming/Erasing Programming/erasing is performed using standard PLD programmers. See “CMOS PLD Pro- gramming Hardware & Software Support” for information on software/programming. 8. Input and I/O Pin-keeper Circuits The ATF22V10C contains internal input and I/O pin-keeper circuits. These circuits allow each ATF22V10C pin to hold its previous value even when it is not being driven by an external source or by the device’s output buffer. This helps to ensure that all logic array inputs are at known valid logic levels. This reduces system power by preventing pins from floating to indeterminate levels. By using pin-keeper circuits rather than pull-up resistors, there is no DC current required to hold the pins in either logic state (high or low). These pin-keeper circuits are implemented as weak feedback inverters, as shown in the Input Diagram below. These keeper circuits can easily be overdriven by standard TTL- or CMOS-com- patible drivers. The typical overdrive current required is 40 µA. Figure 8-1. Input Diagram Table 7-1. Programming/Erasing Parameter Description Typ Max Units t PR Power-up Reset Time 600 1,000 ns VRST Power-up Reset Voltage 3.8 4.5 V |
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