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AT32UC3A3256-ALUR Datasheet(PDF) 4 Page - ATMEL Corporation |
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AT32UC3A3256-ALUR Datasheet(HTML) 4 Page - ATMEL Corporation |
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4 / 961 page  4 32072A–AVR32–03/09 AT32UC3A3 2. Overview 2.1 Block Diagram Figure 2-1. Block Diagram UC CPU NEXUS CLASS 2+ OCD INSTR INTERFACE DATA INTERFACE TIMER/COUNTER 0/1 INTERRUPT CONTROLLER REAL TIME COUNTER PERIPHERAL DMA CONTROLLER 512/256/ 128/64 KB FLASH HSB-PB BRIDGE B HSB-PB BRIDGE A S MM M M M S S S S S M EXTERNAL INTERRUPT CONTROLLER HIGH SPEED BUS MATRIX FAST GPIO 64 KB SRAM PA PB PC PX A[2..0] B[2..0] CLK[2..0] EXTINT[7..0] KPS[7..0] NMI_N GCLK[3..0] XIN32 XOUT32 XIN0 XOUT0 PA PB PC PX RESET_N CAS RAS SDA10 SDCK SDCKE SDCS1 SDWE NCS[5..0] NRD NWAIT NWE0 DATA[15..0] USB HS INTERFACE DMA ID VBOF DH+,DL+ DMACA 32 KHz OSC 115 kHz RCOSC OSC0 PLL0 USART3 SERIAL PERIPHERAL INTERFACE 0/1 TWO-WIRE INTERFACE 0/1 RXD TXD CLK MISO, MOSI NPCS[3..1] SCL SDA USART1 RXD TXD CLK RTS, CTS DSR, DTR, DCD, RI USART0 USART2 RXD TXD CLK RTS, CTS SYNCHRONOUS SERIAL CONTROLLER TX_CLOCK, TX_FRAME_SYNC RX_DATA TX_DATA RX_CLOCK, RX_FRAME_SYNC ANALOG TO DIGITAL CONVERTER AD[7..0] ADVREF WATCHDOG TIMER XIN1 XOUT1 OSC1 PLL1 SCK JTAG INTERFACE MCKO MDO[5..0] MSEO[1..0] EVTI_N EVTO_N TCK TDO TDI TMS POWER MANAGER RESET CONTROLLER ADDR[23..0] SLEEP CONTROLLER CLOCK CONTROLLER CLOCK GENERATOR CONFIGURATION REGISTERS BUS MEMORY PROTECTION UNIT PB PB HSB HS B NWE1 NWE3 NPCS0 LOCAL BUS INTERFACE AUDIO BITSTREAM DAC DATA[1..0] DATAN[1..0] M MULTIMEDIA CARD & MEMORY STICK INTERFACE CLK CMD[1..0] DATA[15..0] S AES S CFCE1 CFCE2 CFRW NANDOE NANDWE S 32KB RAM 32KB RAM DH-,DL- VBG VBUS |
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