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AT32UC3A0256-ALUR Datasheet(PDF) 6 Page - ATMEL Corporation |
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AT32UC3A0256-ALUR Datasheet(HTML) 6 Page - ATMEL Corporation |
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6 / 826 page  6 32058H–AVR32–03/09 AT32UC3A 4.1 Processor and architecture 4.1.1 AVR32 UC CPU • 32-bit load/store AVR32A RISC architecture. – 15 general-purpose 32-bit registers. – 32-bit Stack Pointer, Program Counter and Link Register reside in register file. – Fully orthogonal instruction set. – Privileged and unprivileged modes enabling efficient and secure Operating Systems. – Innovative instruction set together with variable instruction length ensuring industry leading code density. – DSP extention with saturating arithmetic, and a wide variety of multiply instructions. • 3 stage pipeline allows one instruction per clock cycle for most instructions. – Byte, half-word, word and double word memory access. – Multiple interrupt priority levels. • MPU allows for operating systems with memory protection. 4.1.2 Debug and Test system • IEEE1149.1 compliant JTAG and boundary scan • Direct memory access and programming capabilities through JTAG interface • Extensive On-Chip Debug features in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0) Class 2+ – Low-cost NanoTrace supported. • Auxiliary port for high-speed trace information • Hardware support for 6 Program and 2 data breakpoints • Unlimited number of software breakpoints supported • Advanced Program, Data, Ownership, and Watchpoint trace supported 4.1.3 Peripheral DMA Controller • Transfers from/to peripheral to/from any memory space without intervention of the processor. • Next Pointer Support, forbids strong real-time constraints on buffer management. • Fifteen channels – Two for each USART – Two for each Serial Synchronous Controller – Two for each Serial Peripheral Interface – One for each ADC – Two for each TWI Interface 4.1.4 Bus system • High Speed Bus (HSB) matrix with 6 Masters and 6 Slaves handled – Handles Requests from the CPU Data Fetch, CPU Instruction Fetch, PDCA, USBB, Ethernet Controller, CPU SAB, and to internal Flash, internal SRAM, Peripheral Bus A, Peripheral Bus B, EBI. – Round-Robin Arbitration (three modes supported: no default master, last accessed default master, fixed default master) – Burst Breaking with Slot Cycle Limit – One Address Decoder Provided per Master |
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