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R5F64111NLG Datasheet(PDF) 4 Page - Renesas Technology Corp |
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R5F64111NLG Datasheet(HTML) 4 Page - Renesas Technology Corp |
4 / 105 page REJ03B0227-0110 Rev.1.10 Sep 17, 2009 Page 4 of 99 R32C/111 Group 1. Overview Note: 1. Please contact a Renesas sales office to use the optional feature. Table 1.3 R32C/111 Group Performance for the 80-pin Package (1/2) Unit Function Performance CPU Central processing unit R32C/100 Series CPU Core • Basic instructions: 108 • Minimum instruction execution time: 20 ns (f(CPU) = 50 MHz) • Multiplier: 32-bit × 32-bit 64-bit • Multiply-accumulate unit: 32-bit × 32-bit + 64-bit 64-bit • IEEE-754 floating point standard: Single precision • 32-bit barrel shifter • Operating mode: Single-chip mode, memory expansion mode, microprocessor mode (optional (1)) Memory Flash memory: 128/256 Kbytes RAM: 32 Kbytes Data flash: 4 Kbytes × 2 blocks Refer to Table 1.7 for memory size of each product group Voltage Detector Low voltage detector Optional (1) Low voltage detection interrupt Clock Clock generator • 4 circuits (main clock, sub clock, PLL, on-chip oscillator) • Oscillation stop detector: Main clock oscillator stop/re-oscillation detection • Frequency divide circuit: Divide-by-2 to divide-by-24 selectable • Low power modes: Wait mode, stop mode Interrupts Interrupt vectors: 261 External interrupt inputs: NMI, INT × 6, key input × 4 Interrupt priority levels: 7 levels Watchdog Timer 15 bits × 1 (selectable input frequency from prescaler output) DMA DMAC 4 channels • Cycle-steal transfer mode • Request sources: 47 • 2 transfer modes: Single transfer, repeat transfer DMAC II • Can be activated by any peripheral interrupt source • 3 transfer functions: Immediate data transfer, calculation transfer, chained transfer I/O Ports Programmable I/O ports • 1 input-only port • 65 CMOS inputs/outputs • 2 N-channel open drain ports • A pull-up resistor is selectable for every 4 input ports |
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