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AT86RF230-ZU Datasheet(PDF) 11 Page - ATMEL Corporation |
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AT86RF230-ZU Datasheet(HTML) 11 Page - ATMEL Corporation |
11 / 98 page 11 5131E-MCU Wireless-02/09 AT86RF230 6.1 SPI Timing Description The SPI is designed to work in synchronous or asynchronous mode. In synchronous mode, the CLKM output of the radio transceiver is used as the master clock of the microcontroller. In this case the maximum SPI clock frequency is 8 MHz. In asynchronous mode, the SPI master clock (SCLK) is generated by the microcontroller itself. The maximum SPI clock rate is limited to 7.5 MHz using this operating mode. If the clock signal from the radio transceiver pin CLKM is not required, it may be disabled. Figure 6-2 and Figure 6-3 illustrate the SPI timing and introduce its parameters. The corresponding timing parameter definition is given in Table 11-4. Figure 6-2. SPI Timing, Global Map and Definition of Timing Parameters t5, t6, t8 and t9 Figure 6-3. SPI Timing, Detailed View and Definition of Timing Parameters t0 to t4 Bit 7 Bit 6 t1 t0 t2 Bit 5 t4 t3 Bit 7 Bit 6 Bit 5 SCLK SEL MOSI MISO The SPI is based on a byte-oriented protocol and is always a bidirectional communication between master and slave. The SPI master starts the transfer by asserting SEL = L. Then the master generates eight SPI clock cycles to transfer a byte to the radio transceiver (via MOSI). At the same time the slave transmits one byte to the master (via MISO). When the master wants to receive one byte of data from the slave it must also transmit one byte to the slave. All bytes are transferred MSB first. An SPI transaction is finished by releasing SEL = H. A SPI register access consists of two bytes, a Frame Buffer or SRAM access of two or more bytes, as described in section 6.2. SEL = L enables the MISO output driver of the radio transceiver. The MSB of MISO is valid after t1 (see section 11.4 parameter 11.4.3) and is updated at each falling edge of SCLK. If the MISO output driver is disabled, there is no internal pull-up resistor connected to the output. Driving the appropriate signal level must be ensured by the |
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