R8A66156SP

REJ03F0283-0100 Rev.1.00 Sep.14.2009

.

Page 3 of 7

DESCRIPTION OF OPERATION

(1) When power ON, the status of DO and D1~D24 terminals are not determined. These terminals are

turn to high-impedance when "L" is input to the /S terminal.

(2) By the negative edge of /CS, the status of D1~D24 terminals is loaded on shift register 1.

(3) Synchronous to the negative edge of CLK, 24-bit loaded data is serial output from the DO terminal.

(4) Synchronous to the positive edge of CLK, 24-bit serial input data from DI is write into the

shift register 2.

(5) The 25th and following shift clock pulse are ignored and the serial data input operation is stopped.

And the DO terminal becomes high-impedance ("High-Z").

(6) By the positive edge of /CS, input data described in (4) is output to D1~D24 terminals.

(7) Shift register 1 loads the AND tie data of external parallel input data and latched data on parallel output

latch.

(8) If the /CS is changed from "L" to "H" before reaches the 24th bit of CLK, parallel output latch latches

data which has been written on shift register 2 and output it to D1~D24 terminals.

Serial data after

this since is ignored and the DO terminal becomes high-impedance.

(9) Input/output mode set to D1~D24 terminals is done by the serial input data to the DI terminal.

Terminals which "H" is written are set to input, and "L" is written are set to output.

OPERATION TIMING CHART

S

CS

1234

56789

10

23

24

25

CLK

DI

DO

D1

DI1

DO1

D2

DI2

DO2

D24

DI24

DO24

1 Sequence

DO1

DO2

DO3

DO4

DO5

DO6

DO7

DO8

DO9

DO23 DO24

DI1

DI2

DI3

DI4

DI5

DI6

DI7

DI8

DI9

DI23

DI24

High-Z

High-Z

(1)

(2)

(4)

(3)

(5)

(6)

High-Z

High-Z

High-Z