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HMF8M32M8V-120 Datasheet(PDF) 4 Page - Hanbit Electronics Co.,Ltd |
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HMF8M32M8V-120 Datasheet(HTML) 4 Page - Hanbit Electronics Co.,Ltd |
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4 / 11 page  HANBit HMF8M32M8V URL:www.hbe.co.kr 4 HANBit Electronics Co., Ltd. REV.02(August,2002) 3. Maximum Icc current specifications are tested with Vcc=Vcc max ERASE AND PROGRAMMING PERFORMANCE LIMITS PARAMETER MIN. TYP. MAX. UNIT COMMENTS Sector Erase Time - 0.7 15 sec Chip Erase Time 49 sec Excludes 00H programming prior to erasure Byte Programming Time - 9 300 µs Chip Programming Time - 36 108 sec Excludes system-level overhead TSOP CAPACITANCE PARAMETER SYMBOL PARAMETER DESCRIPTION TEST SETUP TYP. MAX UNIT CIN Input Capacitance VIN = 0 6 7.5 pF COUT Output Capacitance VOUT = 0 8.5 12 pF CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF Notes : Test conditions TA = 25 o C, f=1.0 MHz. AC CHARACTERISTICS u Read Only Operations Characteristics PARAMETER SYMBOLS Speed Options JEDEC STANDARD DESCRIPTION TEST SETUP -90 -120 UNIT tAVAV tRC Read Cycle Time Min 90 120 ns tAVQV tACC Address to Output Delay /CE = VIL /OE = VIL Max 90 120 ns tELQV tCE Chip Enable to Output Delay /OE = VIL Max 90 120 ns tGLQV tOE Output Enable to Output Delay Max 35 50 ns tEHQZ tDF Chip Enable to Output High-Z Max 30 30 ns tGHQZ tDF Output Enable to Output High-Z Max 30 30 ns tAXQX tQH Output Hold Time From Addresses, /CE or /OE, Whichever Occurs First Min 0 ns TEST SPECIFICATIONS TEST CONDITION 90 120 UNIT Output load 1TTL gate Output load capacitance,CL (Including jig capacitance) 30 100 pF Input rise and fall times 5 ns Input pulse levels 0.0-3.0 V Input timing measurement reference levels 1.5 V Output timing measurement reference levels 1.5 V |
Similar Part No. - HMF8M32M8V-120 |
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