7

9123B–AUTO–07/09

ATA6871 [Preliminary]

5.

Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating

only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Unless otherwise specified all voltages refer to pin VSSA. Logic Levels: 0 = VSSA, 1 = VDD.

Parameters

Pin

Symbol

Min.

Max.

Unit

Ambient temperature

–40

+85

°C

Junction temperature

–40

+125

°C

Storage temperature

–40

+150

°C

Battery cell voltage

–0.3

+5.5

V

–5.5

+0.3

V

MBAT1

–0.3

+0.3

V

Supply voltage

VDDHV

–0.3

+30

V

Supply voltage (regulator is off)

VDD

–0.3

+5.5

V

Input voltage for logic I/O pins

CHIPONE, CHIPLAST,

CONF0, CONF1,

SCANMODE, CLK,

TEST_HV, TEST_LV,

ENUV, OROUT

V

V

V

–0.3

VDD + 0.3

V

Input voltage for analog low voltage input pins

BIASRES, TEMP_IN

V

–0.3

VDD + 0.3

V

Input voltage for digital high voltage input pins OROUT_IN, STATUS_IN V

VDDHV – 0.3 VDDHV + 0.3

V

Logic output pin STATUS

STATUS

V

STATUS

–0.3

+5.5

V

Input

PD_N

V

PD_N

VDDHV – 5.5 VDDHV + 0.3

V

Output

PD_N_OUT

V

PD_N_OUT

–5.5

+0.3

V

HBM ESD

ANSI/ESD-STM5.1

JESD22-A114

AEC-Q100 (002)

ESD

±2

kV

CDM ESD STM 5.3.1

500

V

CDM ESD STM 5.3.1

VDDHV, CHIPLAST,

CONF1, STATUS_IN

ESD

750

V

Latch Up according to AECQ100-004

LATCH-UP

±100

mA

6.

Thermal Resistance

Parameters

Symbol

Value

Unit

Maximum thermal resistance junction-ambient

R

49

K/W