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9136C–INDCO–10/09

ATA8404/ATA8405 [Preliminary]

4.2

Transmission with ENABLE = High

4.2.1

FSK Mode

The ATA8404/ATA8405 is activated by ENABLE = High, FSK = High, and ASK = Low. The

microcontroller is then switched to external clocking. After typically 0.6 ms, the CLK driver is

activated automatically (i.e., the microcontroller waits until the XTO and CLK are ready). After

another time period of

is switched on with ASK = H. The ATA8404/ATA8405 is then ready for FSK modulation. The

microcontroller starts to switch on and off the capacitor between the crystal load capacitor and

GND by means of pin FSK, thus, changing the reference frequency of the PLL. IF FSK = L the

output frequency is lower, if FSK = H output frequency is higher. After transmission, ASK is

switched to Low and the microcontroller returns back to internal clocking. Then, the

ATA8404/ATA8405 is switched to power-down mode with ENABLE = Low and FSK = Low.

Figure 4-3.

Timing FSK Mode with ENABLE Connected to the Microcontroller

4.2.2

ASK Mode

The ATA8404/ATA8405 is activated by ENABLE = High, FSK = High and ASK = Low. After

activation the microcontroller is switched to external clocking. After typically 0.6 ms, the CLK

driver is activated automatically (the microcontroller waits until the XTO and CLK are ready).

After another time period of

power can then be modulated by means of pin ASK. After transmission, ASK is switched to

Low and the microcontroller returns back to internal clocking. Then, the ATA8404/ATA8405 is

switched to power-down mode with ENABLE = Low and FSK = Low.

FSK

CLK

Power-up,

PA off

ASK

ΔT

XTO

Power-down

Power-up,

PA on

(f

> 250 µs

Power-down

Power-up,

PA off

(f

ENABLE