HANBit

HSD32M64D16R

URL:www.hbe.co.kr

- 8 -

HANBit Electronics Co.,Ltd

REV.1.0 (August.2002).

Notes :

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and

then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

.5. For -1H/1L, tRDL=1CLK and tDAL=1CLK+20ns is also supported .

( recommend : tRDL=2CLK and tDAL=2CLK + 20ns.)

AC CHARACTERISTICS

(AC operating conditions unless otherwise noted)

-1H

-1L

-13

PARAMETER

SYMBO

L

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

NOTE

CAS latency=3

10

10

7.5

CLK cycle time

CAS latency=2

10

1000

12

1000

-

1000

ns

1

CAS latency=3

6

6

5.4

CLK to valid

output delay

CAS latency=2

6

7

-

ns

1,2

CAS latency=3

3

3

2.7

``Output data

hold time

CAS latency=2

3

3

-

ns

1,2

CLK high pulse width

3

3

2.5

ns

3

CLK low pulse width

3

3

2.5

ns

3

Input setup time

2

2

1.5

ns

3

Input hold time

1

1

0.8

ns

3

CLK to output in Low-Z

1

1

1

ns

2

CAS latency=3

6

6

5.4

ns

1

CLK to output

in Hi-Z

CAS latency=2

6

7

-

ns

1

Notes :

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf) = 1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered

i.e., [(tr + tf)/2-1]ns should be added to the parameter.