HANBit

HSD128M72B9K

HANBit Electronics Co.,Ltd.

REV.0.0(January. 2003)

7

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

VERSION

PARAMETER

SYMBOL

-13

-12

-10

-10L

UNIT

NOTE

Row active to row active delay

15

16

20

20

ns

1

RAS to CAS delay

20

20

20

20

ns

1

Row precharge time

20

20

20

20

ns

1

45

48

50

50

ns

1

Row active time

100

ns

Row cycle time

65

68

70

70

ns

1

Last data in to row precharge

2

CLK

2.5

Last data in to Active delay

-

5

Last data in to new col. address delay

1

CLK

2

Last data in to burst stop

1

CLK

2

Col. address to col. address delay

1

CLK

3

CAS latency=3

2

Number of valid output data

CAS latency=2

-

1

ea

4

Notes :

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and

then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

AC CHARACTERISTICS

(AC operating conditions unless otherwise noted)

-13

-12

-10

-10L

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

NOTE

CAS

latency=3

7.5

8

10

10

CLK cycle time

CAS

latency=2

-

1000

-

1000

10

1000

12

1000

ns

1

CAS

latency=3

5.4

6

6

6

CLK to valid

output delay

CAS

latency=2

-

-

6

7

ns

1,2

Output data

hold time

CAS

latency=3

2.7

3

3

3

ns

2