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HI-6121PQI Datasheet(PDF) 11 Page - Holt Integrated Circuits |
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HI-6121PQI Datasheet(HTML) 11 Page - Holt Integrated Circuits |
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11 / 116 page  mode command is legal, the RT “responds in form” and updates status. If a mode command is illegal, the RT asserts Message Error status and (if non-broadcast) transmits only its Status Word without associated data word. Later in this data sheet, the section “RT Message Responses, Options & Exceptions” fully describes terminal response for each mode code value, command word bit state, and option settings. If this bit is high, undefined mode code commands are treated as invalid: There is no RT recognition of an invalid command, no RT command response, and no status updating for the benefit of following “transmit status” or “transmit last command” mode commands. 2 NOTICE2 If this bit is high, the terminal stores data associated with broadcast commands separately from data associated with non-broadcast commands to meet the requirements of MIL-STD-1553B Notice 2. If this bit is low, broadcast command data is stored in the same buffer as non-broadcast command data. 1 SMCP Simplified Mode Command Processing. When asserted the device applies simplified processing for all valid mode code commands. The later section entitled “Mode Command Processing” describes this option. (0x0001) This 16-bit register is Read-Write and is fully maintained by the host. All bits are active high. This register is cleared after pin Master Reset, but is unaffected by SRST software reset. 15 TOSEL1 Time-Out Select for RT-RT Receive Commands. 14 TOSEL0 These bits select the “no response” time-out for RT-RT receive commands. Message error occurs when the transmitting Remote Terminal fails to begin transmission before time-out occurs. Time interval boundaries are defined in RT validation test plan Figure 8 “RT-RT Timeout Measurement.” MIL-STD-1553B stipulates that 54 to 60us is the acceptable range for time-out. However, longer time-out options are provided for systems using long buses and/or utilizing bus repeaters that add delay to bus traffic. RT-RT time-out can be selected from the following options: 1 1 150 us 1 0 125 us 0 1 100 us 0 0 57 us (default after pin master reset) 13 TRXDB Temporary Receive Data Buffer. Setting this bit enables a temporary data buffer for all receive commands. When enabled, the RT stores received data words in a 32-word data buffer during message processing. Upon error-free message completion, all saved words are written to data buffer memory in a burst. When the temporary receive data buffer is disabled, the RT writes each received data word to the subaddress data buffer memory as it is received. Should message error occur during data word reception, this mode results in loss of data integrity, as vaild data from the prior command is partially overwritten by data from a message with error. MIL-STD-1553 states that data should be disregarded for messages CONFIGURATION REGISTER 2 Bit No. Mnemonic Function TOSEL1 TOSEL0 RT-RT Time-Out T/R 0 SSRD8 Single-Strobe Read for 8-Bit Parallel Bus Mode. This bit only applies to HI-6120 (not HI-6121) and only applies when the parallel host bus is configured for 8-bit bus width. When performing 2-byte read accesses of external memory, some microprocessors with 8-bit bus assert individual Read Enable (or ) pulses for high and low bytes. Other microprocessors assert a single, wider Read Enable (or ) pulse, while simply changing the low address bit (A0 / ) to access the two bytes. For this last case, the SSRD8 bit should be set when writing device configuration, before register or RAM readback is performed. STROBE STROBE LB MR MR REGISTERS, Cont. MSB LSB 15 14 13 12 11 10 9876543210 X X X XX HOLT INTEGRATED CIRCUITS 11 HI-6120, HI-6121 |
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