FIFO

LOAD

CONTROL

CONTROL BITS

CR2, CR6-8

/

SPI INTERFACE

32 BIT SHIFT REGISTER

CONTROLBITS

CR0, CR1

CLOCK

OPTION

CLOCK

ACLK

BIT

COUNTER

AND

END OF

SEQUENCE

PARITY

CHECK

32ND

BIT

DATA

BIT CLOCK

WORD GAP

WORD GAP

TIMER

BIT CLOCK

END

START

SEQUENCE

CONTROL

ERROR

CLOCK

ERROR

DETECTION

SHIFT REGISTER

SHIFT REGISTER

NULL

ZEROS

SHIFT REGISTER

ONES

EOS

FIGURE 2.

RECEIVER BLOCK DIAGRAM

LABEL /

DECODE

COMPARE

256-BIT

LABEL

LOOK-UP

TABLE

32X32

FIFO

RFLAG

SCK

CS

SI

SO

0

X

0

X

Load FIFO

1

No

0

X

Ignore data

1

Yes

0

X

Load FIFO

0

X

1

No

Ignore data

0

X

1

Yes

Load FIFO

1

Yes

1

No

Ignore data

1

No

1

Yes

Ignore data

1

No

1

No

Ignore data

1

Yes

1

Yes

Load FIFO

CR2

ARINC word

CR6

ARINC word

FIFO

matches

bits 10, 9

Enabled

match

CR7, 8

label

RECEIVER PARITY

The receiver parity circuit counts Ones received, including the

parity bit. If the result is odd, a "0" appears in the 32nd bit.

RETRIEVING DATA

Once 32 valid bits are recognized, the receiver logic generates an

End of Sequence (EOS).

Depending on the state of Control

Register bits CR2, CR6, CR7 and CR8, the received 32-bit ARINC

word is then checked for correct decoding and label match before

it is loaded into the 32 x 32 Receive FIFO. ARINC words that do

not match required 9th and 10th ARINC bit and do not have a label

match are ignored and are not loaded into the Receive FIFO. The

adjacent table describes this operation.

FUNCTIONAL DESCRIPTION (cont.)

TABLE 3. FIFO LOADING CONTROL

HI-3585

HOLT INTEGRATED CIRCUITS

6